MPC8280 datasheet(103/1386 Pages) FREESCALE

103 / 1386 page

Overview

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

1-9

NOTE

A bar over a signal name indicates that the signal is active low—for

example, BB (bus busy). Active-low signals are referred to as asserted

(active) when they are low and negated when they are high. Signals that are

not active low, such as TSIZ[0–3] (transfer size signals) are referred to as

asserted when they are high and negated when they are low.

Figure 1-2. MPC8280 External Signals

VCCSYN/GNDSYN/VCCSYN1//VDDH/

VDD/VSS ⎯⎯⎯> 100

<⎯⎯> A[0–31]

PCI_PAR/L_A14

<⎯⎯> 1

<⎯⎯> TT[0–4]

SMI/PCI_FRAME/L_A15

<⎯⎯> 14 <⎯⎯> TSIZ[0–3]

PCI_TRDY/L_A16

<⎯⎯> 11 <⎯⎯> TBST

CKSTOP_OUT/PCI_IRDY/L_A17

<⎯⎯> 11 <⎯⎯> GBL/IRQ1

PCI_STOP/L_A18

<⎯⎯> 11 <⎯⎯> CI/BADDR29/IRQ2

PCI_DEVSEL/L_A19

<⎯⎯> 11 <⎯⎯> WT/BADDR30/IRQ3

PCI_IDSEL/L_A20

<⎯⎯> 11 <⎯⎯⎯ L2_HIT/IRQ4

PCI_PERR/L_A21

<⎯⎯> 11 <⎯⎯> CPU_BG/BADDR31/IRQ5/CINT

PCI_SERR/L_A22

<⎯⎯> 11 ⎯⎯⎯> CPU_DBG

PCI_REQ0/L_A23

<⎯⎯> 11 ⎯⎯⎯> CPU_BR

CPCI_HS_ES/PCI_REQ1/L_A24

<⎯⎯> 11 <⎯⎯> BR

PCI_GNT0/L_A25

<⎯⎯> 11 <⎯⎯> BG

CPCI_HS_LED/PCI_GNT1/L_A26

<⎯⎯⎯ 11 <⎯⎯> ABB/IRQ2

CPCI_HS_ENUM/PCI_CLK/L_A27

<⎯⎯> 11 <⎯⎯> TS

CORE_SRESET/PCI_RST/L_A28

<⎯⎯> 11 <⎯⎯> AACK

PCI_INTA/L_A29

<⎯⎯> 11 <⎯⎯> ARTRY

PCI_REQ2/L_A30

<⎯⎯> 11 <⎯⎯> DBG

DLLOUT/L_A31

<⎯⎯> 11 <⎯⎯> DBB/IRQ3

PCI_AD[0–31]/LCL_D[0–31]

<⎯⎯> 32

<⎯⎯> D[0–63]

PCI_C/BE[0–3]/LCL_DP[0–3]

<⎯⎯> 41 <⎯⎯> NC/DP0/RSRV/EXT_BR2

PCI_CFG[3–0]/LBS[0–3]/

LSDDQM[0–3]/LWE[0–3]

<⎯⎯⎯ 4

<⎯⎯> IRQ1/DP1/EXT_BG2

<⎯⎯> IRQ2/DP2/TLBISYNC/EXT_DBG2

<⎯⎯> IRQ3/DP3/CKSTP_OUT/EXT_BR3

PCI_MODCK_H0/LGPL0/LSDA10

<⎯⎯⎯ 11 <⎯⎯> IRQ4/DP4/CORE_SRESET/EXT_BG3

PCI_MODCK_H1/LGPL1/LSDWE

<⎯⎯⎯ 11 <⎯⎯> IRQ5/DP5/TBEN/EXT_DBG3/CINT

PCI_MODCK_H2/LGPL2/LSDRAS/LOE

<⎯⎯⎯ 11 <⎯⎯> IRQ6/DP6/CSE0

PCI_MODCK_H3/LGPL3/LSDCAS

<⎯⎯⎯ 11 <⎯⎯> IRQ7/DP7/CSE1

LPBS/LGPL4/LUPMWAIT/LGTA

<⎯⎯> 11 <⎯⎯> PSDVAL

PCI_MODCK/LGPL5

<⎯⎯> 11 <⎯⎯> TA

LWR

<⎯⎯> 11 <⎯⎯> TEA

<⎯⎯> IRQ0/NMI_OUT

PA[0–31]

<⎯⎯> 32

<⎯⎯> IRQ7/INT_OUT/APE

PB[4–31]

<⎯⎯> 28

⎯⎯⎯> CS[0–9]

PC[0–31]

<⎯⎯> 32

<⎯⎯> CS[10]/BCTL1

PD[4–31]

<⎯⎯> 28

<⎯⎯> CS[11]/AP[0]

⎯⎯⎯> BADDR[27–28]

PCI_RST/PORESET

⎯⎯⎯> 1

⎯⎯⎯> ALE

RSTCONF

⎯⎯⎯> 11 ⎯⎯⎯> BCTL0

HRESET

<⎯⎯> 18 ⎯⎯⎯> PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

SRESET

<⎯⎯> 11 ⎯⎯⎯> PSDA10/PGPL0

QREQ

<⎯⎯⎯ 11 ⎯⎯⎯> PSDWE/PGPL1

XFC

⎯⎯⎯> 11 ⎯⎯⎯> POE/PSDRAS/PGPL2

CLKIN1

⎯⎯⎯> 11 ⎯⎯⎯> PSDCAS/PGPL3

TRIS

⎯⎯⎯> 11 <⎯⎯> PGTA/PUPMWAIT/PGPL4/PPBS

BNKSEL[0]/TC[0]/AP[1]/MODCK1

<⎯⎯> 11 ⎯⎯⎯> PSDAMUX/PGPL5

BNKSEL[1]/TC[1]/AP[2]/MODCK2

<⎯⎯> 1

<⎯⎯⎯ TMS

BNKSEL[2]/TC[2]/AP[3]/MODCK3

<⎯⎯> 11 <⎯⎯⎯ TDI

PCI_MODE

⎯⎯⎯> 11 <⎯⎯⎯ TCK

CLKIN2

⎯⎯⎯> 11 <⎯⎯⎯ TRST

⎯⎯⎯> 2

⎯⎯⎯> TDO

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