MPC8280 datasheet(291/1386 Pages) FREESCALE

291 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-15

Due to the performance degradation, misaligned memory operations should be avoided. In addition to the

double-word straddle boundary condition, the processor’s address translation logic can generate

substantial exception overhead when the load/store multiple and load/store string instructions access

misaligned data. It is strongly recommended that software attempt to align code and data where possible.

8.4.3.6

Effect of Port Size on Data Transfers

The MPC8280 can transfer operands through its 64-bit data port. If the transfer is controlled by the internal

memory controller, the MPC8280 can support 8-, 16-, 32-, and 64-bit data port sizes as demonstrated in

Figure 8-6. The bus requires that the portion of the data bus used for a transfer to or from a particular port

size be fixed. A 64-bit port must reside on data bus bits D[0–63], a 32-bit port must reside on bits D[0–31],

a 16-bit port must reside on bits D[0–15], and an 8-bit port must reside on bits D[0–7]. The MPC8280

always tries to transfer the maximum amount of data on all bus cycles: for a word operation, it always

assumes the port is 64 bits wide when beginning the bus cycle; for burst and extended byte cycles, a 64-bit

bus is assumed.

Figure 8-6. shows the device connections on the data bus. Table 8-8 lists the bytes required on the data bus

for read cycles.

Table 8-7. Unaligned Data Transfer Example (4-Byte Example)

Program Size of

Word (4 bytes)

TSIZ[1–3]

A[29–31]

Data Bus Byte Lanes

D0...

...D31

D32...

...D63

Aligned

100

000

1 A: Byte lane used

AAA

—2

2 —: Byte lane not used

———

Misaligned—1st access

0 1 1

0 0 1

—

————

2nd access

0 0 1

1 0 0

————

———

Misaligned—1st access

0 1 0

——

————

2nd access

0 1 0

1 0 0

————

——

Misaligned—1st access

0 0 1

0 1 1

———

————

2nd access

0 1 1

1 0 0

————

—

Aligned

1 0 0

————

Misaligned—1st access

0 1 1

1 0 1

—————

2nd access

0 0 1

0 0 0

———————

Misaligned—1st access

0 1 0

1 1 0

——————

2nd access

0 1 0

0 0 0

——————

Misaligned—1st access

0 0 1

1 1 1

———————

2nd access

0 1 1

0 0 0

—————

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