MPC8280 datasheet(289/1386 Pages) FREESCALE

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The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-13

NOTE

The basic coherency size of the bus is 32 bytes for the processor

(cache-block size). Data transfers that cross an aligned 32-byte boundary

must present a new address onto the bus at that boundary for proper snoop

operation, or must operate as non-coherent with respect to the MPC8280.

8.4.3.4

Burst Ordering During Data Transfers

During burst transfers, 32 bytes of data (one cache block) are transferred to or from the cache. Burst write

transfers are performed zero double-word-first. However, because burst reads are performed

critical-double-word-first, a burst-read transfer may not start with the first double word of the cache block

and the cache-block-fill operation may wrap around the end of the cache block. Table 8-5 describes

MPC8280 burst ordering.

Each data beat is terminated with an assertion of TA.

Negated

0 0 1 1

3 Bytes

—

Core and DMA

Negated

0 1 0 0

4 Bytes

Word

Core and DMA

Negated

0 1 0 1

5 Bytes

Extended 5 bytes

SDMA (MPC8280 only)

Negated

0 1 1 0

6 Bytes

Extended 6 bytes

SDMA (MPC8280 only)

Negated

0 1 1 1

7 Bytes

Extended 7 bytes

SDMA (MPC8280 only)

Negated

0 0 0 0

8 Bytes

Double-word (maximum data bus size)

Core and DMA

Negated

1 0 0 1

16 Bytes

Extended double double word

SDMA (MPC8280 only)

Negated

1 0 1 0

24 Bytes

Extended triple double word

SDMA (MPC8280 only)

Asserted

0 0 1 0

32 bytes

Quad double-word (4 maximum data

beats)

Core and DMA

Table 8-5. Burst Ordering

Data Transfer

Double Word Starting Address:

A[27–28] = 001

1 A[27–28] specifies the first double word of the 32-byte block being transferred; any subsequent double words must

wrap-around the block. A[29–31] are always 0b000 for burst transfers by the MPC8280.

A[27–28] = 01

A[27–28] = 10

A[27–28] = 11

1st data beat

DW02

2 DWx represents the double word that would be addressed by A[27–28] = x if a nonburst transfer were performed.

DW1

DW2

DW3

2nd data beat

DW1

DW2

DW3

DW0

3rd data beat

DW2

DW3

DW0

DW1

4th data beat

DW3

DW0

DW1

DW2

Table 8-4. Transfer Size Signal Encoding (continued)

TBST

TSIZ[0–3]

Transfer Size

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