CS42448 datasheet(45/64 Pages) CIRRUS

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DS648F2

CS42448

6.5.4

ADC Digital Interface Format (ADC_DIF[2:0])

Default = 110

Function:

These bits select the digital interface format used for the ADC serial port. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options

are detailed in the section “CODEC Digital Interface Formats” on page 31. Refer to Table 9, “Serial Audio

Interface Channel Allocations,” on page 34.

Note:

The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.

6.6

ADC Control & DAC De-Emphasis (Address 05h)

6.6.1

ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset

value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter

Characteristics” on page 13.

Right Justified, 16-bit data

Figure 17

One-Line #1, 20-bit

Figure 18

One-Line #2, 24-bit

Figure 19

TDM Mode, 24-bit (slave only)

Figure 20

Reserved

ADC_DIF2 ADC_DIF1 ADC_DIF0

Description

Format

Figure

Left Justified, up to 24-bit data

Figure 16

I²S, up to 24-bit data

Figure 15

Right Justified, 24-bit data

Figure 17

Right Justified, 16-bit data

Figure 17

One-Line #1, 20-bit

Figure 18

One-Line #2, 24-bit

Figure 19

TDM Mode, 24-bit (slave only)

Figure 20

Reserved

Table 13. ADC Digital Interface Formats

432

ADC1-2_HPF

FREEZE

ADC3_HPF

FREEZE

DAC_DEM

ADC1

SINGLE

ADC2

SINGLE

ADC3

SINGLE

AIN5_MUX

AIN6_MUX

DAC_DIF2 DAC_DIF1

DAC_DIF0

Description

Format

Figure

Table 12. DAC Digital Interface Formats

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