CS42448 datasheet(44/64 Pages) CIRRUS

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DS648F2

CS42448

6.5

Interface Formats (Address 04h)

6.5.1

Freeze Controls (FREEZE)

Default = 0

Function:

This function will freeze the previous settings of, and allow modifications to be made to the channel mutes,

the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the

FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously,

enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

6.5.2

Auxiliary Digital Interface Format (AUX_DIF)

Default = 0

0 - Left Justified

1 - I²S

Function:

This bit selects the digital interface format used for the AUX Serial Port. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options

are detailed in Figures 23-24.

6.5.3

DAC Digital Interface Format (DAC_DIF[2:0])

Default = 110

Function:

These bits select the digital interface format used for the DAC Serial Port. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format; the options are

detailed in the section “CODEC Digital Interface Formats” on page 31.

Refer to Table 9, “Serial Audio Interface Channel Allocations,” on page 34.

Ratio (xFs)

MFreq2

MFreq1

MFreq0

Description

SSM

DSM

QSM

1.0290 MHz to 12.8000 MHz

256

N/A

1.5360 MHz to 19.2000 MHz

384

N/A

2.0480 MHz to 25.6000 MHz

512

256

N/A

3.0720 MHz to 38.4000 MHz

768

384

N/A

4.0960 MHz to 51.2000 MHz

1024

512

256

Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats

543

FREEZE

AUX_DIF

DAC_DIF2

DAC_DIF1

DAC_DIF0

ADC_DIF2

ADC_DIF1

ADC_DIF0

DAC_DIF2 DAC_DIF1

DAC_DIF0

Description

Format

Figure

Left Justified, up to 24-bit data

Figure 16

I²S, up to 24-bit data

Figure 15

Right Justified, 24-bit data

Figure 17

Table 12. DAC Digital Interface Formats

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