CS42448 datasheet(31/64 Pages) CIRRUS

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DS648F2

CS42448

4.5

CODEC Digital Interface Formats

The ADC and DAC serial ports support the I²S, Left-Justified, Right-Justified, One-Line Mode (OLM) and

TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figures 15-19. Data is

clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. The serial

bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronously derived from the master clock and be

equal to 256x, 128x, 64x, 48x or 32x Fs, depending on the interface format selected and desired speed

mode. One-Line Mode #1 and One-Line Mode #2 will operate in master or slave mode. Refer to Table 5 for

required clock ratios. The SCLK to sample rate (LRCK) ratios are shown in Tables 5 through 8.

I²S, Left-Justified, Right-Justified

Ratio

SSM

DSM

QSM

MCLK/LRCK

256x, 384x, 512x,

768x, 1024x

128x, 192x, 256x, 384x,

512x

64x, 96x, 128x, 192x,

256x

SCLK/LRCK (Slave Mode)

32x, 48x, 64x

SCLK/LRCK (Master Mode)

64x

Table 5. I²S, LJ, RJ Clock Ratios

OLM #1

SSM

DSM

QSM

MCLK/LRCK

256x, 384x, 512x,

768x, 1024x

256x, 384x, 512x

N/A

SCLK/LRCK (Slave Mode)

128x

N/A

SCLK/LRCK (Master Mode)

128x

N/A

Table 6. OLM#1 Clock Ratios

OLM #2

SSM

DSM

QSM

MCLK/LRCK

256x, 384x, 512x,

768x, 1024x

256x, 384x, 512x

N/A

SCLK/LRCK (Slave Mode)

256x

N/A

SCLK/LRCK (Master Mode)

256x

N/A

Table 7. OLM#2 Clock Ratios

TDM

SSM

DSM

QSM (DAC only)

MCLK/LRCK

256x, 384x, 512x,

768x, 1024x

256x, 384x, 512x

256x

SCLK/LRCK (Slave Mode)

256X

SCLK/LRCK (Master Mode)

N/A

Table 8. TDM Clock Ratios

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