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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS42448 датащи(PDF) 18 Page - Cirrus Logic |
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CS42448 датащи(HTML) 18 Page - Cirrus Logic |
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18 / 64 page  18 DS648F2 CS42448 SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.) Parameters (Note 20) Symbol Min Max Units Slave Mode RST pin Low Pulse Width (Note 16) 1 -ms MCLK Frequency 0.512 50 MHz MCLK Duty Cycle (Note 17) 45 55 % Input Sample Rate (LRCK) Single-Speed Mode Double-Speed Mode (Note 18) Quad-Speed Mode (Note 19) Fs Fs Fs 4 50 100 50 100 200 kHz kHz kHz LRCK Duty Cycle 45 55 % SCLK Duty Cycle 45 55 % SCLK High Time tsckh 8- ns SCLK Low Time tsckl 8- ns LRCK Rising Edge to SCLK Rising Edge tfss tlcks 5- ns SCLK Rising Edge to LRCK Falling Edge tfsh 16 - ns SCLK Falling Edge to ADC_SDOUT Output Valid tdpd -35 ns DAC_SDIN Setup Time Before SCLK Rising Edge tds 3- ns DAC_SDIN Hold Time After SCLK Rising Edge tdh 5- ns DAC_SDIN Hold Time After SCLK Rising Edge tdh1 5- ns ADC_SDOUT Hold Time After SCLK Rising Edge tdh2 10 - ns ADC_SDOUT Valid Before SCLK Rising Edge tdval 15 - ns Master Mode Output Sample Rate (LRCK) All Speed Modes Fs -MCLK / 256 kHz LRCK Duty Cycle 45 55 % SCLK Frequency - 64 x Fs MHz SCLK Duty Cycle 45 55 % LRCK Edge to SCLK Rising Edge tlcks -5 ns SCLK Falling Edge to ADC_SDOUT Output Valid tdpd -35 ns DAC_SDIN Setup Time Before SCLK Rising Edge tds 3- ns DAC_SDIN Hold Time After SCLK Rising Edge tdh1 5- ns ADC_SDOUTx DAC_SDINx t ds SCLK LRCK MSB t dh t sckh t sckl t dpd MSB t lcks MSB-1 MSB-1 ADC_SDOUT1 DAC_SDIN1 t ds SCLK (input) LRCK (input) MSB t dh1 t sckh t sckl t dval MSB-1 MSB MSB-1 t fsh t fss t dh2 Figure 4. Serial Audio Interface Slave Mode Timing Figure 5. TDM Serial Audio Interface Timing |
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