CS42448 datasheet(36/64 Pages) CIRRUS

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DS648F2

CS42448

4.7.2

I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should

be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the

CS42448 is being reset.

The signal timings for a read and write cycle are shown in Figure 24 and Figure 25. A Start condition is

defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while

the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the

CS42448 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42448,

the chip address field, which is the first byte sent to the CS42448, should match 10010 followed by the

settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the

next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-

eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-

ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an

acknowledge bit. The ACK bit is output from the CS42448 after each input byte is read, and is input to the

CS42448 from the microcontroller after each transmitted byte.

MA P

MSB

LSB

DATA

by te 1

by te n

R/W

AD D R ESS

CH IP

ADDRESS

CH IP

CD IN

CC L K

CD OU T

MSB

LSB MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 23. Control Port Timing in SPI Mode

24 25

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 AD1 AD0 0

SDA

INCR

16 17 18

10 11

13 14 15

27 28

DATA +n

Figure 24. Control Port Timing, I²C Write

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