CS42448 datasheet(51/64 Pages) CIRRUS

51 / 64 page

DS648F2

CS42448

6.13 When enabled, these bits will invert the signal polarity of their respective channels.Status Control

(Address 18h)

6.13.1 Interrupt Pin Control (INT[1:0])

Default = 00

00 - Active high; high output indicates interrupt condition has occurred

01 - Active low, low output indicates an interrupt condition has occurred

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.

11 - Reserved

Function:

Determines how the Interrupt pin (INT) will indicate an interrupt condition.

For DAC and ADC clock errors, the INT pin is set to “Level Active Mode” and will become active during

the clock error. For the ADCx_OVFL error, the INT pin is set to Level Active Mode and will become active

during the overflow error.

6.14 Status (Address 19h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated

mask register will always be “0” in this register.

6.14.1 DAC CLOCK ERROR (DAC_CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to DAC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes

active during the error condition. See “System Clocking” on page 30 for valid clock ratios.

6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to ADC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes

active during the error condition. See “System Clocking” on page 30 for valid clock ratios.

6.14.3 ADC Overflow (ADCX_OVFL)

Default = x

Function:

Indicates that there is an over-range condition anywhere in the CS42448 ADC signal path of each of the

associated ADC’s. These status flags become active on the arrival of the error condition.

432

Reserved

INT1

INT0

Reserved

DAC_CLK Error

ADC_CLK Error

ADC3_OVFL

ADC2_OVFL

ADC1_OVFL

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