CS42448 datasheet(30/64 Pages) CIRRUS

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DS648F2

CS42448

De-emphasis is only available in Single-Speed Mode. Please see “DAC De-Emphasis Control

(DAC_DEM)” on page 46 for de-emphasis control.

4.4

System Clocking

The CODEC (ADC & DAC) serial audio interface ports operate both as a slave or master. The serial ports

accept externally generated clocks in slave mode and will generate synchronous clocks derived from an in-

put master clock in master mode. In the TDM format the ADC and DAC serial ports will only operate as a

slave. In OLM #2 the serial ports will accept or output a 256Fs SCLK. See the registers “DAC Functional

Mode (DAC_FM[1:0])” on page 43 and “ADC Functional Mode (ADC_FM[1:0])” on page 43 for setting up

master/slave mode.

The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be

an integer multiple of, and synchronous with, the system sample rate, Fs.

The required integer ratios, along with some common frequencies, are illustrated in tables Tables 2 to 4.

The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency

(MFREQ[2:0])” on page 43.

Sample Rate

(kHz)

MCLK (MHz)

256x

384x

512x

768x

1024x

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

Table 2. Single-Speed Mode Common Frequencies

Sample Rate

(kHz)

MCLK (MHz)

128x

192x

256x

384x

512x

8.1920

12.2880

16.3840

24.5760

32.7680

88.2

11.2896

16.9344

22.5792

33.8688

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

Table 3. Double-Speed Mode Common Frequencies

Sample Rate

(kHz)

MCLK (MHz)

64x

96x

128x

192x

256x

176.4

11.2896

16.9344

22.5792

33.8688

45.1584

192

12.2880

18.4320

24.5760

36.8640

49.1520

Table 4. Quad-Speed Mode Common Frequencies

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

3.183kHz

10.61kHz

Figure 14. De-Emphasis Curve

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