WM8804 datasheet(26/66 Pages) WOLFSON

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WM8804

Production Data

PD Rev 4.1 September 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R28

AIFRX

1Ch

AIF_MS

Audio Interface Mode Select

0 = Slave mode – MCLK Input

1 = Master mode – MCLK Output

Table 25 Audio Interface Mode Select

When MCLK is configured as an output, the MCLK source and rate can be selected using the control

bits shown in Table 26. The MCLK rate select can only be used when the MCLK output source is

selected as the PLL clock. If the oscillator clock is selected as the PLL source, the MCLK frequency

is equal to the oscillator clock frequency.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLL5

07h

MCLKDIV

MCLK Divider Select

(Only valid when CLK2 is selected

as MCLK output source)

See Table 27 for MCLKDIV

configuration in PLL user mode.

See Table 28 for MCLKDIV

configuration in PLL S/PDIF receive

mode.

PLL6

08h

MCLKSRC

MCLK Output Source select

0 = Select CLK2

1 = Select OSCCLK

Table 26 Master Clock Output Control

F2 TO CLK1 DIVISION FACTOR

F2 TO CLK2 DIVISION FACTOR

CLKOUTDIV[1:0]

MCLKDIV

FREQMODE[1:0]

÷2

÷4

÷8

÷2

÷4

÷2

÷4

÷8

÷16

÷4

÷8

÷4

÷8

÷16

÷32

÷8

÷16

÷6

÷12

÷24

÷48

÷12

÷24

Table 27 PLL User Mode Clock Divider Configuration

CLKOUTDIV[1:0]

CLK1 FREQUENCY

MCLKDIV

CLK2 FREQUENCY

512fs

256fs

128fs

64fs

Table 28 PLL S/PDIF Receive Mode Clock Divider Configuration

Note: The fs values shown above are relative to the S/PDIF recovered sample rate.

When MCLK is configured as an input, the reference clock rate for the S/PDIF transmitter (when the

digital audio interface received data is configured as the S/PDIF transmitter data source) is controlled

by the frequency of the MCLK signal at the MCLK pin.

Refer to the “Digital Audio Interface” datasheet section for details of configuring MCLK for appropriate

digital audio interface operation.

CLOCK OUTPUT (CLKOUT)

The high-drive clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be

used as a clock source pin for providing the central clock reference for an audio system.

The CLKOUT clock source can be selected from either the OSCCLK or CLK1 signals. The control

bits for the CLKOUT signal are shown in Table 29.

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