WM8804 datasheet(44/66 Pages) WOLFSON

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WM8804

Production Data

PD Rev 4.1 September 2007

DIGITAL AUDIO INTERFACE

Audio data is transferred to and from the WM8804 via the digital audio interface. Data from the digital

audio interface transmitter may be passed to the S/PDIF transmitter or data from the S/PDIF receiver

may be output on the digital audio interface receiver. The digital audio interface can be powered

down using the AIFPD register bit described in Table 53.

BIT

LABEL

DEFAULT

DESCRIPTION

R30

PWRDN

1Eh

AIFPD

Digital Audio Interface Power

Down

1 = Power down

0 = Power up

Table 53 Digital Audio Interface Power Down Control

MASTER AND SLAVE MODES

The audio interface operates in either slave or master mode, selectable using the AIF_MS bit (see

Table 55). In both master and slave modes DIN is always an input and DOUT is always an output.

The default is slave mode.

In slave mode (AIF_MS=0), LRCLK and BCLK are inputs. DIN and LRCLK are sampled on the rising

edge of BCLK. Data output, DOUT, changes on the falling edge of BCLK and the polarity of BCLK

may be reversed independently on the transmit and receive sides of the interface using the

AIFRX_BCP and AIFTX_BCP control bits, see Table 56.

In master mode (AIF_MS=1), LRCLK and BCLK are generated by the WM8804. As in slave mode,

DIN is sampled on the rising edge of BCLK, and DOUT changes on the falling edge of BCLK and the

polarity of BCLK may be reversed the transmit and receive sides of the interface with the

AIFRX_BCP and AIFTX_BCP control bits.

The frequencies of LRCLK are derived from MCLK and are dependant on the MCLKDIV control bit.

Table 54 shows the settings for MCLKDIV for common sample rates and MCLK frequencies.

MASTER CLOCK (MCLK) FREQUENCY

(MHZ)

128fs

256fs

SAMPLING

RATE

(LRCLK)

MCLKDIV = 1

MCLKDIV = 0

32kHz

4.096

8.192

44.1kHz

5.6448

11.2896

48kHz

6.144

12.288

96kHz

12.288

24.576

192kHz

24.576

Unavailable

Table 54 Master Mode LRCLK Frequency Selection

BCLK is also generated by the WM8804. The frequency of BCLK depends on the mode of operation.

In 128fs mode (MCLKDIV = 1) BCLK = MCLK/2. In 256fs mode (MCLKDIV = 0) BCLK = MCLK/4.

However if DSP mode is selected as the audio interface mode then BCLK=MCLK. Note that DSP

mode cannot be used in 128fs mode for data word lengths greater than 16-bits.

Master/slave mode is selected with the following register:

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R28

AIFRX

1Ch

AIF_MS

Audio Interface Master/Slave Mode Select

0 = Slave mode – MCLK, LRCLK and BCLK

are inputs

1 = Master mode – MCLK, LRCLK and BCLK

are outputs

Table 55 Master/Slave Mode Select Register

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