WM8804 datasheet(54/66 Pages) WOLFSON

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WM8804

Production Data

PD Rev 4.1 September 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FREQMODE[1:0]

PLL Post-scale Divider Select

Selects the PLL output divider value in

conjunction with MCLKDIV and CLKOUTDIV.

Refer to Table 23 for details of FREQMODE

operation.

Note: FREQMODE[1:0] bits are

automatically set in S/PDIF Receive Mode.

FRACEN

Integer/Fractional PLL Mode Select

0 = Integer PLL (PLL_N value used, PLL_K

value ignored)

1 = Fractional PLL (both PLL_N and PLL_K

values used)

Note: FRACEN must be set to enable the

fractional PLL when using S/PDIF Receive

Mode.

PLL5

07h

MCLKDIV

MCLK Divider Select

(Only valid when CLK2 is selected as MCLK

output source)

See Table 23 for MCLKDIV configuration in

PLL user mode.

See Table 28 for MCLKDIV configuration in

PLL S/PDIF receive mode.

5:4

CLKOUTDIV[1:0]

CLKOUT Divider Select

(Only valid when CLK1 is selected as CLKOUT

output source)

See Table 23 for CLKOUTDIV[1:0]

configuration in PLL user mode.

See Table 28 for CLKOUTDIV[1:0]

configuration in PLL S/PDIF receive mode.

CLKOUTSRC

CLKOUT Pin Source Select

0 = Select CLK1

1 = Select OSCCLK

CLKOUTDIS

CLKOUT Pin Disable

0 = Pin Disabled (Pin tri-stated)

1 = Pin Enabled

FILLMODE

Fill Mode Select

Determines S/PDIF receiver action when

corrupt or invalid data is detected:

0 = Data from S/PDIF receiver remains static

at last valid sample.

1 = Data from S/PDIF receiver is output as all

zeros.

ALWAYSVALID

Always Valid Select

Used to ignore the INVALID flag.

0 = Use INVALID flag.

1 = Ignore INVALID flag.

PLL6

08h

MCLKSRC

MCLK Output Source Select

0 = Select CLK2

1 = Select OSCCLK

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