WM8804 datasheet(41/66 Pages) WOLFSON

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Production Data

WM8804

PD Rev 4.1 September 2007

Where the INT_N has been asserted by an update signal (UPD_NON_AUDIO, UPD_CPY_N,

UPD_REC_FREQ, UPD_UNLOCK or UPD_DEEMPH) the S/PDIF Status Register (SPDSTAT) can

be interrogated to establish the updated value of the flag.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AUDIO_N

Audio Status Flag

Recovered channel status bit-1.

0 = Data word represents audio PCM samples.

1 = Data word does not represent audio PCM samples.

PCM_N

Non-PCM Flag

Indicates that non-audio code (defined in IEC-61937) has

been detected.

0 = Sync code not detected.

1 = Sync code detected – received data is not audio PCM.

CPY_N

Non-Copyright Flag

Recovered Channel Status bit-2.

0 = Copyright is asserted for this data.

1 = Copyright is not asserted for this data.

DEEMPH

De-emphasis Flag

Recovered Channel Status bit-3.

0 = Copyright is asserted for this data.

1 = Copyright is not asserted for this data.

5:4

REC_FREQ

[1:0]

Recovered Frequency Flag

Indicates recovered S/PDIF clock frequency:

00 = 192kHz

01 = 96kHz or 88.2kHz

10 = 48kHz or 44.1kHz

11 = 32kHz

R12

SPDSTAT

0Ch

(read-only)

UNLOCK

Unlock Flag

Indicates that the S/PDIF Rx clock recovery circuit is

unlocked.

0 = Locked onto incoming S/PDIF stream.

1 = Not locked onto the incoming S/PDIF stream.

Table 49 S/PDIF Status Register

The interrupt and update signals used to generate INT_N can be masked at the users discretion. The

MASK register bit (Table 50) prevents flags from asserting INT_N and from updating the Interrupt

Status Register.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R10

INTMASK

0Ah

7:0

MASK[7:0]

00000000

Interrupt Mask Enable

When a flag is masked, it does not update the Interrupt Status

0 = unmask, 1 = mask.

MASK[0] = mask control for UPD_UNLOCK

MASK[1] = mask control for INT_INVALID

MASK[2] = mask control for INT_CSUD

MASK[3] = mask control for INT_TRANS_ERR

MASK[4] = mask control for UPD_NON_AUDIO

MASK[5] = mask control for UPD_CPY_N

MASK[6] = mask control for UPD_DEEMPH

MASK[7] = mask control for UPD_REC_FREQ

Table 50 Interrupt Mask Control Register

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