PIC18F4685-ISLASHSP datasheet(140/484 Pages) MICROCHIP

140 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 138

Preliminary

10.4

PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt Trigger

input buffers. Each pin is individually configurable as an

input or output.

Three of the PORTD pins are multiplexed with outputs

P1A, P1B, P1C and P1D of the Enhanced CCP1

(ECCP1) module. The operation of these additional

PWM output pins is covered in greater detail in

Section 16.0 “Enhanced Capture/Compare/PWM

(ECCP1) Module”.

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.6 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

EXAMPLE 10-4:

INITIALIZING PORTD

Note:

PORTD is only available on PIC18F4682/

4685 devices.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

Note:

When the Enhanced PWM mode is used

with either dual or quad outputs, the PSP

functions of PORTD are automatically

disabled.

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

CLRF

LATD

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

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