PIC18F4685-ISLASHSP datasheet(51/484 Pages) MICROCHIP

51 / 484 page

Preliminary

DS39761B-page 49

PIC18F2682/2685/4682/4685

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

TOSU

2682 2685 4682 4685

---0 0000

---0 uuuu(3)

TOSH

2682 2685 4682 4685

0000 0000

uuuu uuuu(3)

TOSL

2682 2685 4682 4685

0000 0000

uuuu uuuu(3)

STKPTR

2682 2685 4682 4685

00-0 0000

uu-0 0000

uu-u uuuu(3)

PCLATU

2682 2685 4682 4685

---0 0000

---u uuuu

PCLATH

2682 2685 4682 4685

0000 0000

uuuu uuuu

PCL

2682 2685 4682 4685

0000 0000

PC + 2(2)

TBLPTRU

2682 2685 4682 4685

--00 0000

--uu uuuu

TBLPTRH

2682 2685 4682 4685

0000 0000

uuuu uuuu

TBLPTRL

2682 2685 4682 4685

0000 0000

uuuu uuuu

TABLAT

2682 2685 4682 4685

0000 0000

uuuu uuuu

PRODH

2682 2685 4682 4685

xxxx xxxx

uuuu uuuu

PRODL

2682 2685 4682 4685

xxxx xxxx

uuuu uuuu

INTCON

2682 2685 4682 4685

0000 000x

0000 000u

uuuu uuuu(1)

INTCON2

2682 2685 4682 4685

1111 -1-1

uuuu -u-u(1)

INTCON3

2682 2685 4682 4685

11-0 0-00

uu-u u-uu(1)

INDF0

2682 2685 4682 4685

N/A

POSTINC0

2682 2685 4682 4685

N/A

POSTDEC0

2682 2685 4682 4685

N/A

PREINC0

2682 2685 4682 4685

N/A

PLUSW0

2682 2685 4682 4685

N/A

FSR0H

2682 2685 4682 4685

---- 0000

---- uuuu

FSR0L

2682 2685 4682 4685

xxxx xxxx

uuuu uuuu

WREG

2682 2685 4682 4685

xxxx xxxx

uuuu uuuu

INDF1

2682 2685 4682 4685

N/A

POSTINC1

2682 2685 4682 4685

N/A

POSTDEC1

2682 2685 4682 4685

N/A

PREINC1

2682 2685 4682 4685

N/A

PLUSW1

2682 2685 4682 4685

N/A

FSR1H

2682 2685 4682 4685

---- 0000

---- uuuu

FSR1L

2682 2685 4682 4685

xxxx xxxx

uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.

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