 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
PIC18F4685-I/SP датащи(PDF) 84 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F4685-I/SP датащи(HTML) 84 Page - Microchip Technology |
|
|
84 / 484 page  PIC18F2682/2685/4682/4685 DS39761B-page 82 Preliminary © 2007 Microchip Technology Inc. RXF1SIDL SID2 SID1 SID0 —EXIDEN —EID17 EID16 xxx- x-xx 56, 303 RXF1SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 RXF0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 304 RXF0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 304 RXF0SIDL SID2 SID1 SID0 —EXIDEN —EID17 EID16 xxx- x-xx 56, 303 RXF0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 56, 304 B5D7(8) B5D77 B5D76 B5D75 B5D74 B5D73 B5D72 B5D71 B5D70 xxxx xxxx 56, 300 B5D6(8) B5D67 B5D66 B5D65 B5D64 B5D63 B5D62 B5D61 B5D60 xxxx xxxx 56, 300 B5D5(8) B5D57 B5D56 B5D55 B5D54 B5D53 B5D52 B5D51 B5D50 xxxx xxxx 56, 300 B5D4(8) B5D47 B5D46 B5D45 B5D44 B5D43 B5D42 B5D41 B5D40 xxxx xxxx 56, 300 B5D3(8) B5D37 B5D36 B5D35 B5D34 B5D33 B5D32 B5D31 B5D30 xxxx xxxx 56, 300 B5D2(8) B5D27 B5D26 B5D25 B5D24 B5D23 B5D22 B5D21 B5D20 xxxx xxxx 56, 300 B5D1(8) B5D17 B5D16 B5D15 B5D14 B5D13 B5D12 B5D11 B5D10 xxxx xxxx 56, 300 B5D0(8) B5D07 B5D06 B5D05 B5D04 B5D03 B5D02 B5D01 B5D00 xxxx xxxx 56, 300 B5DLC(8) Receive mode — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B5DLC(8) Transmit mode —TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 B5EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 56, 299 B5EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 56, 299 B5SIDL(8) Receive mode SID2 SID1 SID0 SRR EXID —EID17 EID16 xxxx x-xx 56, 298 B5SIDL(8) Transmit mode SID2 SID1 SID0 — EXIDE —EID17 EID16 xxx- x-xx 56, 298 B5SIDH(8) SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx x-xx 56, 297 B5CON(8) Receive mode RXFUL RXM1 RXRTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 56, 296 B5CON(8) Transmit mode TXBIF TXABT TXLARB TXERR TXREQ RTREN TXPRI1 TXPRI0 0000 0000 56, 296 B4D7(8) B4D77 B4D76 B4D75 B4D74 B4D73 B4D72 B4D71 B4D70 xxxx xxxx 56, 300 B4D6(8) B4D67 B4D66 B4D65 B4D64 B4D63 B4D62 B4D61 B4D60 xxxx xxxx 56, 300 B4D5(8) B4D57 B4D56 B4D55 B4D54 B4D53 B4D52 B4D51 B4D50 xxxx xxxx 56, 300 B4D4(8) B4D47 B4D46 B4D45 B4D44 B4D43 B4D42 B4D41 B4D40 xxxx xxxx 57, 300 B4D3(8) B4D37 B4D36 B4D35 B4D34 B4D33 B4D32 B4D31 B4D30 xxxx xxxx 57, 300 B4D2(8) B4D27 B4D26 B4D25 B4D24 B4D23 B4D22 B4D21 B4D20 xxxx xxxx 57, 300 B4D1(8) B4D17 B4D16 B4D15 B4D14 B4D13 B4D12 B4D11 B4D10 xxxx xxxx 57, 300 B4D0(8) B4D07 B4D06 B4D05 B4D04 B4D03 B4D02 B4D01 B4D00 xxxx xxxx 56, 300 B4DLC(8) Receive mode — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 56, 301 B4DLC(8) Transmit mode —TXRTR — — DLC3 DLC2 DLC1 DLC0 -x-- xxxx 56, 302 B4EIDL(8) EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 57, 299 B4EIDH(8) EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 57, 299 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
