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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F4685-I/SP датащи(PDF) 43 Page - Microchip Technology |
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PIC18F4685-I/SP датащи(HTML) 43 Page - Microchip Technology |
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43 / 484 page  © 2007 Microchip Technology Inc. Preliminary DS39761B-page 41 PIC18F2682/2685/4682/4685 4.0 RESET The PIC18F2682/2685/4682/4685 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset during execution e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 24.2 “Watchdog Timer (WDT)”. A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers”. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”. FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR VDD OSC1 WDT Time-out VDD Rise Detect OST/PWRT INTRC(1) POR Pulse OST 10-Bit Ripple Counter PWRT Chip_Reset 11-Bit Ripple Counter Enable OST(2) Enable PWRT Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. Brown-out Reset BOREN RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 1024 Cycles 65.5 ms 32 μs MCLRE |
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