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PIC18F4685-I/SP датащи(PDF) 57 Page - Microchip Technology |
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PIC18F4685-I/SP датащи(HTML) 57 Page - Microchip Technology |
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57 / 484 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39761B-page 55 PIC18F2682/2685/4682/4685 TXB2D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu 0uuu uuuu TXB2DLC 2682 2685 4682 4685 -x-- xxxx -u-- uuuu -u-- uuuu TXB2EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu TXB2SIDH 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu TXB2CON 2682 2685 4682 4685 0000 0-00 0000 0-00 uuuu u-uu RXM1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM1SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXM1SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXM0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL 2682 2685 4682 4685 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. |
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