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PIC18F4685-I/SP датащи(PDF) 55 Page - Microchip Technology |
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PIC18F4685-I/SP датащи(HTML) 55 Page - Microchip Technology |
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55 / 484 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39761B-page 53 PIC18F2682/2685/4682/4685 BRGCON3 2682 2685 4682 4685 00-- -000 00-- -000 uu-- -uuu BRGCON2 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu BRGCON1 2682 2685 4682 4685 0000 0000 0000 0000 uuuu uuuu CANCON 2682 2685 4682 4685 1000 000- 1000 000- uuuu uuu- CANSTAT 2682 2685 4682 4685 100- 000- 100- 000- uuu- uuu- RXB0D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu RXB0EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON 2682 2685 4682 4685 000- 0000 000- 0000 uuu- uuuu RXB1D7 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC 2682 2685 4682 4685 -xxx xxxx -uuu uuuu -uuu uuuu RXB1EIDL 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH 2682 2685 4682 4685 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL 2682 2685 4682 4685 xxxx x-xx uuuu u-uu uuuu u-uu TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. |
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