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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18F4685-I/SP датащи(PDF) 81 Page - Microchip Technology |
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PIC18F4685-I/SP датащи(HTML) 81 Page - Microchip Technology |
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81 / 484 page  © 2007 Microchip Technology Inc. Preliminary DS39761B-page 79 PIC18F2682/2685/4682/4685 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 132 PORTA RA7(6) RA6(6) RA5 RA4 RA3 RA2 RA1 RA0 xx00 0000 52, 129 ECANCON MDSEL1 MDSEL0 FIFOWM EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 0001 000 52, 280 TXERRCNT TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 0000 0000 52, 285 RXERRCNT REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0000 0000 52, 294 COMSTAT Mode 0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281 COMSTAT Mode 1 — RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN -000 0000 52, 281 COMSTAT Mode 2 FIFOEMPT Y RXBnOVFL TXBO TXBP RXBP TXWARN RXWARN EWARN 0000 0000 52, 281 CIOCON — — ENDRHI CANCAP — — — — --00 ---- 52, 315 BRGCON3 WAKDIS WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 00-- -000 53, 314 BRGCON2 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 0000 0000 53, 313 BRGCON1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000 53, 312 CANCON Mode 0 REQOP2 REQOP1 REQOP0 ABAT WIN2(7) WIN1(7) WIN0(7) —(7) 1000 000- 53, 276 CANCON Mode 1 REQOP2 REQOP1 REQOP0 ABAT —(7) —(7) —(7) —(7) 1000 ---- 53, 276 CANCON Mode 2 REQOP2 REQOP1 REQOP0 ABAT FP3(7) FP2(7) FP1(7) FP0(7) 1000 0000 53, 276 CANSTAT Mode 0 OPMODE2 OPMODE1 OPMODE0 —(7) ICODE3(7) ICODE2(7) ICODE1(7) —(7) 100- 000- 53, 277 CANSTAT Modes 1, 2 OPMODE2 OPMODE1 OPMODE0 EICODE4(7) EICODE3(7) EICODE2(7) EICODE1(7) EICODE0(7) 1000 0000 53, 277 RXB0D7 RXB0D77 RXB0D76 RXB0D75 RXB0D74 RXB0D73 RXB0D72 RXB0D71 RXB0D70 xxxx xxxx 53, 293 RXB0D6 RXB0D67 RXB0D66 RXB0D65 RXB0D64 RXB0D63 RXB0D62 RXB0D61 RXB0D60 xxxx xxxx 53, 293 RXB0D5 RXB0D57 RXB0D56 RXB0D55 RXB0D54 RXB0D53 RXB0D52 RXB0D51 RXB0D50 xxxx xxxx 53, 293 RXB0D4 RXB0D47 RXB0D46 RXB0D45 RXB0D44 RXB0D43 RXB0D42 RXB0D41 RXB0D40 xxxx xxxx 53, 293 RXB0D3 RXB0D37 RXB0D36 RXB0D35 RXB0D34 RXB0D33 RXB0D32 RXB0D31 RXB0D30 xxxx xxxx 53, 293 RXB0D2 RXB0D27 RXB0D26 RXB0D25 RXB0D24 RXB0D23 RXB0D22 RXB0D21 RXB0D20 xxxx xxxx 53, 293 RXB0D1 RXB0D17 RXB0D16 RXB0D15 RXB0D14 RXB0D13 RXB0D12 RXB0D11 RXB0D10 xxxx xxxx 53, 293 RXB0D0 RXB0D07 RXB0D06 RXB0D05 RXB0D04 RXB0D03 RXB0D02 RXB0D01 RXB0D00 xxxx xxxx 53, 293 RXB0DLC — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 -xxx xxxx 53, 293 RXB0EIDL EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 xxxx xxxx 53, 292 RXB0EIDH EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 xxxx xxxx 53, 292 RXB0SIDL SID2 SID1 SID0 SRR EXID —EID17 EID16 xxxx x-xx 53, 292 RXB0SIDH SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 xxxx xxxx 53, 291 RXB0CON Mode 0 RXFUL RXM1 RXM0(7) —(7) RXRTRRO(7) RXBODBEN(7) JTOFF(7) FILHIT0(7) 000- 0000 53, 288 RXB0CON Mode 1, 2 RXFUL RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 0000 0000 53, 288 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D74 RXB1D73 RXB1D72 RXB1D71 RXB1D70 xxxx xxxx 53, 293 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D64 RXB1D63 RXB1D62 RXB1D61 RXB1D60 xxxx xxxx 53, 293 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685 devices; individual unimplemented bits should be interpreted as ‘—’. 4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 7: CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. |
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