SC28L92 datasheet(30/44 Pages) PHILIPS

30 / 44 page

Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

when the CPU reads the receive FIFO, only if (after this read) there

are no more characters in the FIFO – the Rx FIFO becomes empty.

SRB—Channel B Status Register

The bit definitions for this register are identical to the bit definitions

for SRA, except that all status applies to the Channel B receiver and

transmitter and the corresponding inputs and outputs.

OPCR—Output Port Configuration Register

OPCR OUTPUT PORT CONFIGURATION REGISTER

Addr

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OPCR

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

0x0D

0 = OPR[7]

0 = OPR[6]

0 = OPR[5]

0 = OPR[4]

00 = OPR[3]

00 = OPR[2]

1 = TxRDY B

1 = TxRDY A

1 = RxRDY/FFULL B

1 = RxRDY/FFULL A

01 = C/T OUTPUT

01 = TxCA(16X)

10 = TxCB(1X)

10 = TxCA(1X)

11 = RxCB(1X)

11 = RxCA(1X)

OPCR[7]—OP7 Output Select

This bit programs the OP7 output to provide one of the following:

The complement of OPR[7].

The Channel B transmitter interrupt output which is the

complement of ISR[4]. When in this mode OP7 acts as an

open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[6]—OP6 Output Select

This bit programs the OP6 output to provide one of the following:

The complement of OPR[6].

The Channel A transmitter interrupt output which is the

complement of ISR[0]. When in this mode OP6 acts as an

open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[5]—OP5 Output Select

This bit programs the OP5 output to provide one of the following:

The complement of OPR[5].

The Channel B receiver interrupt output which is the

complement of ISR[5]. When in this mode OP5 acts as an

open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[4]—OP4 Output Select

This field programs the OP4 output to provide one of the following:

The complement of OPR[4].

The Channel A receiver interrupt output which is the

complement of ISR[1]. When in this mode OP4 acts as an

open-drain output. Note that this output is not masked by the

contents of the IMR.

OPCR[3:2]—OP3 Output Select

This bit programs the OP3 output to provide one of the following:

The complement of OPR[3].

The counter/timer output, in which case OP3 acts as an

open-drain output. In the timer mode, this output is a square

wave at the programmed frequency. In the counter mode,

the output remains High until terminal count is reached, at

which time it goes Low. The output returns to the High state

when the counter is stopped by a stop counter command.

Note that this output is not masked by the contents of the

IMR.

The 1X clock for the Channel B transmitter, which is the

clock that shifts the transmitted data. If data is not being

transmitted, a free running 1X clock is output.

The 1X clock for the Channel B receiver, which is the clock

that samples the received data. If data is not being received,

a free running 1X clock is output.

OPCR[1:0]—OP2 Output Select

This field programs the OP2 output to provide one of the following:

The complement of OPR[2].

The 16X clock for the Channel A transmitter. This is the

clock selected by CSRA[3:0], and will be a 1X clock if

CSRA[3:0] = 1111.

The 1X clock for the Channel A transmitter, which is the

clock that shifts the transmitted data. If data is not being

transmitted, a free running 1X clock is output.

The 1X clock for the Channel A receiver, which is the clock

that samples the received data. If data is not being received,

a free running 1X clock is output.

SC28L92 датащи(PDF) 30 Page - NXP Semiconductors

SC28L92 датащи(HTML) 30 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL