Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

23

For the receiver these bits control the number of FIFO positions

filled when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

MR0[5:4]—Tx interrupt fill level.

Table 4. Transmitter FIFO interrupt fill level

MR0(3) = 0 (8 bytes)

MR0[5:4]

Interrupt Condition

00

8 bytes empty (Tx EMPTY)

01

4 or more bytes empty

10

6 or more bytes empty

11

1 or more bytes empty (Tx RDY)

Table 4a. Transmitter FIFO interrupt fill

level MR0(3) = 1 (16 bytes)

MR0[5:4]

Interrupt Condition

00

16 bytes empty (Tx EMPTY)

01

8 or more bytes empty

10

12 or more bytes empty

11

1 or more bytes empty (Tx RDY)

For the transmitter these bits control the number of FIFO positions

empty when the transmitter will attempt to interrupt. After the reset

the transmit FIFO has 8 bytes empty. It will then attempt to interrupt

as soon as the transmitter is enabled. The default setting of the MR0

bits (5:4) condition the transmitter to attempt to interrupt only when it

is completely empty. As soon as one byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

MR0[3]—Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4

MR0[2:0]—These bits are used to select one of the six baud rate

groups.

See Table 5 for the group organization.

000 Normal mode

001 Extended mode I

100 Extended mode II

Other combinations of MR2[2:0] should not be used

Note: MR0[3:0] are not used in channel B and should be set to 0.

MR1A Mode Register 1

Addr

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR1A/

MR1B

Rx CONTROLS

RTS

RxINT

BIT 1

ERROR

MODE

PARITY MODE

PARITY TYPE

BITS PER

CHARACTER

0x00

0x08

0 = No

1 = Yes

0 = RxRDY

1 = FFULL

0 = Char

1 = Block

00 = With Parity

01 = Force Parity

10 = No Parity

11 = Multi-drop Mode

0 = Even

1 = Odd

00 = 5

01 = 6

10 = 7

11 = 8

NOTE:

In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.

MR1A is accessed when the Channel A MR pointer points to MR1.

The pointer is set to MR1 by RESET or by a ‘set pointer’ command

applied via CR command 1. After reading or writing MR1A, the

pointer will point to MR2A.

MR1A[7]—Channel A Receiver Request-to-Send Control

(Flow Control)

This bit controls the deactivation of the RTSAN output (OP0) by the

receiver. This output is normally asserted by setting OPR[0] and

negated by resetting OPR[0]. Proper automatic operation of flow

control requires OPR[0] (channel A) or OPR[1] (channel B) to be set

to logical 1.

MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a ‘1’

This is the beginning of the reception of the ninth byte. If the FIFO is

not read before the start of the tenth or 17th byte, an overrun

condition will occur and the tenth or 17th or 17th byte will be lost.

However, the bit in OPR[0] is not reset and RTSAN will be asserted

again when an empty FIFO position is available. This feature can be

used for flow control to prevent overrun in the receiver by using the

RTSAN output signal to control the CTSN input of the transmitting

device.

MR1[6]—Bit 1 of the receiver interrupt control. See description

under MR0[6].

MR1A[5]—Channel A Error Mode Select

This bit select the operating mode of the three FIFOed status bits

(FE, PE, received break) for Channel A. In the ‘character’ mode,

status is provided on a character-by-character basis; the status

applies only to the character at the top of the FIFO. In the ‘block’

mode, the status provided in the SR for these bits is the

accumulation (logical-OR) of the status for all characters coming to

the top of the FIFO since the last ‘reset error’ command for

Channel A was issued.

MR1A[4:3|—Channel A Parity Mode Select

If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data MR1A[4:3] = 11 selects Channel A to operate in the

special multi-drop mode described in the Operation section.

MR1A[2]—Channel A Parity Type Select

This bit selects the parity type (odd or even) if the ‘with parity’ mode

is programmed by MR1A[4:3], and the polarity of the forced parity bit

if the ‘force parity’ mode is programmed. It has no effect if the ‘no