SC28L92 datasheet(19/44 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

status bits (see below) are ‘popped’ thus emptying a FIFO position

for new data.

A disabled receiver with data in its FIFO may generate an interrupt

(see “Receiver Status Bits”, below). Its status bits remain active and

its watchdog, if enabled, will continue to operate.

Receiver Status Bits

In addition to the data word, three status bits (parity error, framing

error, and received break) are also appended to each data character

in the FIFO. The overrun error, MR1(5), is not FIFOed.

Status can be provided in two ways, as programmed by the error

mode control bit in the mode register. In the ‘character’ mode, status

is provided on a character-by-character basis; the status applies

only to the character at the top of the FIFO. In the ‘block’ mode, the

status provided in the SR for these three bits is the logical-OR of the

status for all characters coming to the top of the FIFO since the last

‘reset error’ from the command register was issued. In either mode

reading the SR does not affect the FIFO. The FIFO is ‘popped’ only

when the RxFIFO is read. Therefore the status register should be

read prior to reading the FIFO.

If the FIFO is full when a new character is received, that character is

held in the receive shift register until a FIFO position is available. If

an additional character is received while this state exits, the

contents of the FIFO are not affected; the character previously in the

shift register is lost and the overrun error status bit (SR[4]) will be

set-upon receipt of the start bit of the new (overrunning) character.

The receiver can control the deactivation of RTS. If programmed to

operate in this mode, the RTSN output will be negated when a valid

start bit was received and the FIFO is full. When a FIFO position

becomes available, the RTSN output will be re-asserted (set low)

automatically. This feature can be used to prevent an overrun, in the

receiver, by connecting the RTSN output to the CTSN input of the

transmitting device.

If the receiver is disabled, the FIFO characters can be read.

However, no additional characters can be received until the receiver

is enabled again. If the receiver is reset, the FIFO and all of the

receiver status, and the corresponding output ports and interrupt are

reset. No additional characters can be received until the receiver is

enabled again.

Receiver Reset and Disable

Receiver disable stops the receiver immediately—data being

assembled in the receiver shift register is lost. Data and status in the

FIFO is preserved and may be read. A re-enable of the receiver

after a disable will cause the receiver to begin assembling

characters at the next start bit detected.

A receiver reset will discard the present shift register date, reset the

receiver ready bit (RxRDY), clear the status of the byte at the top of

the FIFO and re-align the FIFO read/write pointers.

Watchdog

A ‘watchdog timer’ is associated with each receiver. Its interrupt is

enabled by MR0[7]. The purpose of this timer is to alert the control

processor that characters are in the RxFIFO which have not been

read. This situation may occur at the end of a transmission when the

last few characters received are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the receiver shift register to the

RxFIFO or a read of the RxFIFO is executed.

Receiver Time-out Mode

In addition to the watch dog timer described in the receiver section,

the counter/timer may be used for a similar function. Its

programmability, of course, allows much greater precision of time

out intervals.

The time-out mode uses the received data stream to control the

counter. Each time a received character is transferred from the shift

not received before the counter reaches zero count, the counter

ready bit is set, and an interrupt can be generated. This mode can

be used to indicate when data has been left in the RxFIFO for more

than the programmed time limit. Otherwise, if the receiver has been

programmed to interrupt the CPU when the receive FIFO is full, and

the message ends before the FIFO is full, the CPU may not know

there is data left in the FIFO. The CTU and CTL value would be

programmed for just over one character time, so that the CPU would

be interrupted as soon as it has stopped receiving continuous data.

This mode can also be used to indicate when the serial line has

been marking for longer than the programmed time limit. In this

case, the CPU has read all of the characters from the FIFO, but the

last character received has started the count. If there is no new data

during the programmed time interval, the counter ready bit will get

set, and an interrupt can be generated.

The time-out mode is enabled by writing the appropriate command

to the command register. Writing an ‘Ax’ to CRA or CRB will invoke

the time-out mode for that channel. Writing a ‘Cx’ to CRA or CRB

will disable the time-out mode. The time-out mode should only be

used by one channel at once, since it uses the C/T. If, however, the

time-out mode is enabled from both receivers, the time-out will occur

only when both receivers have stopped receiving data for the

time-out period. CTU and CTL must be loaded with a value greater

than the normal receive character period. The time-out mode

disables the regular START/STOP Counter commands and puts the

ca/T into counter mode under the control of the received data

stream. Each time a received character is transferred from the shift

reloaded with the value in CTU and CTL and then restarted on the

next C/T clock. If the C/T is allowed to end the count before a new

character has been received, the counter ready bit, ISR[3], will be

set. If IMR[3] is set, this will generate an interrupt. Receiving a

character after the C/T has timed out will clear the counter ready bit,

ISR[3], and the interrupt. Invoking the ‘Set Time-out Mode On’

command, CRx = ‘Ax’, will also clear the counter ready bit and stop

the counter until the next character is received.

Time Out Mode Caution

When operating in the special time out mode, it is possible to

generate what appears to be a “false interrupt”, i.e., an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

Multi-drop Mode (9-bit or Wake-Up)

The DUART is equipped with a wake up mode for multi-drop

applications. This mode is selected by programming bits

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