Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

28

CRA—Channel A Command Register

CRA is a register used to supply commands to Channel A. Multiple commands can be specified in a single write to CRA as long as the

commands are non-conflicting, e.g., the ‘enable transmitter’ and ‘reset transmitter’ commands cannot be specified in a single command word.

CR COMMAND REGISTER

Addr

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CRA/B

MISCELLANEOUS COMMANDS

Disable Tx

Enable Tx

Disable Rx

Enable Rx

0x02

0x0A

See Text of Channel Command Register

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

NOTES:

Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.

CRA[7:4]—Miscellaneous Commands

Execution of the commands in the upper four bits of this register

must be separated by 3 X1 clock edges. Other reads or writes

(including writes tot he lower four bits) may be inserted to achieve

this separation.

CRA[7:4]—Commands

0000

No command.

0001

Reset MR pointer. Causes the Channel A MR pointer to

point to MR1.

0010

Reset receiver. Resets the Channel A receiver as if a

hardware reset had been applied. The receiver is

disabled and the FIFO is flushed.

0011

Reset transmitter. Resets the Channel A transmitter as

if a hardware reset had been applied.

0100

Reset error status. Clears the Channel A Received

Break, Parity Error, and Overrun Error bits in the status

register (SRA[7:4]). Used in character mode to clear OE

status (although RB, PE and FE bits will also be

cleared) and in block mode to clear all error status after

a block of data has been received.

0101

Reset Channel A break change interrupt. Causes the

Channel A break detect change bit in the interrupt

status register (ISR[2]) to be cleared to zero

0110

Start break. Forces the TxDA output Low (spacing). If

the transmitter is empty the start of the break condition

will be delayed up to two bit times. If the transmitter is

active the break begins when transmission of the

character is completed. If a character is in the TxFIFO,

the start of the break will be delayed until that character,

or any other loaded subsequently are transmitted. The

transmitter must be enabled for this command to be

accepted.

0111

Stop break. The TxDA line will go High (marking) within

two bit times. TxDA will remain High for one bit time

before the next character, if any, is transmitted.

1000

Assert RTSN. Causes the RTSN output to be asserted

(Low).

1001

Negate RTSN. Causes the RTSN output to be negated

(High)

1010

Set Timeout Mode On. The receiver in this channel will

restart the C/T as each receive character is transferred

from the shift register to the RxFIFO. The C/T is placed

in the counter mode, the START/STOP counter

commands are disabled, the counter is stopped, and

the Counter Ready Bit, ISR[3], is reset. (See also

Watchdog timer description in the receiver section.)

1011

Set MR pointer to ‘0’

1100

Disable Timeout Mode. This command returns control

of the C/T to the regular START/STOP counter

commands. It does not stop the counter, or clear any

pending interrupts. After disabling the timeout mode, a

‘Stop Counter’ command should be issued to force a

reset of the ISR(3) bit

1101

Not used.

1110

Power Down Mode On. In this mode, the DUART

oscillator is stopped and all functions requiring this

clock are suspended. The execution of commands

other than disable power down mode (1111) requires a

X1/CLK. While in the power down mode, do not issue

any commands to the CR except the disable power

down mode command. The contents of all registers will

be saved while in this mode. . It is recommended that

the transmitter and receiver be disabled prior to placing

the DUART into power down mode. This command is in

CRA only.

1111

Disable Power Down Mode. This command restarts the

oscillator. After invoking this command, wait for the

oscillator to start up before writing further commands to

the CR. This command is in CRA only. For maximum

CRA[3]—Disable Channel A Transmitter

This command terminates transmitter operation and reset the

TxDRY and TxEMT status bits. However, if a character is being

transmitted or if a character is in the TxFIFO when the transmitter is

disabled, the transmission of the character(s) is completed before

assuming the inactive state.

CRA[2]—Enable Channel A Transmitter

Enables operation of the Channel A transmitter. The TxRDY and

TxEMT status bits will be asserted if the transmitter is idle.