SC28L92 datasheet(22/44 Pages) PHILIPS

22 / 44 page

Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

CTPL

– COUNTER TIMER PRESET REGISTER, LOWER

Bits 7:0

8 LSB of the BRG Timer divisor.

ACR

– AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL

Bit 7

Bit 6:4

Bit 3

Bit 2

Bit 1

Bit 0

Baud Group

Counter Timer mode and clock select

Enable IP3

Enable IP2

Enable IP1

Enable IP0

IPCR

– INPUT PORT CHANGE REGISTER

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Delta IP3

Delta IP2

Delta IP1

Delta IP0

State of IP3

State of IP2

State of IP1

State of IP0

IPR

– INPUT PORT REGISTER

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

State of IP

State of IP 6

State of IP 5

State of IP 4

State of IP 3

State of IP 2

State of IP1

State of IP 0

SOPR – SET THE OUTPUT PORT BITS (OPR)

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Set OP 7

Set OP 6

Set OP 5

Set OP 4

Set OP 3

Set OP 2

Set OP 1

Set OP 0

ROPR – RESET OUTPUT PORT BITS (OPR)

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Reset OP 7

Reset OP 6

Reset OP 5

Reset OP 4

Reset OP 3

Reset OP 2

Reset OP 1

Reset OP 0

OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND

ARE CONTROLLED BY THE MR REGISTER)

Bit 7

BIT 6

BIT 5

BIT 4

BIT(3:2)

BIT(1:0)

Configure OP7

Configure OP6

Configure OP5

Configure OP4

Configure OP3

Configure OP2

MR0A Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.

Addr

Bit 7

BIT 6

BITS 5:4

BIT 3

BIT 2

BIT 1

BIT 0

MR0A/

MR0B

WATCHDOG

RxINT BIT 2

TxINT (1:0)

FIFO SIZE

BAUD RATE

EXTENDED II

TEST 2

BAUD RATE

EXTENDED 1

0x00

0x08

0 = Disable

1 = Enable

See Tables in

MR0

description

See Table 4

0 = 8 byte FIFO

1 = 16 byte FIFO

0 = Normal

1 = Extend II

Set to 0

0 = Normal

1 = Extend

MR0[7]—This bit controls the receiver watch dog timer. 0 = disable,

1 = enable. When enabled, the watch dog timer will generate a

receiver interrupt if the receiver FIFO has not been accessed within

64 bit times of the receiver 1X clock. This is used to alert the control

processor that data is in the RxFIFO that has not been read. This

situation may occur when the byte count of the last part of a

message is not large enough to generate an interrupt.

MR0[6]—Bit 2 of receiver FIFO interrupt level. This bit along with Bit

6 of MR1 sets the fill level of the FIFO that generates the receiver

interrupt.

MR0[6] MR1[6] Note that this control is split between MR0 and

MR1. This is for backward compatibility to the SC2692 and

SCN2681.

Table 3. Receiver FIFO interrupt fill level

(MR0(3) = 0 (8 bytes)

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (Rx RDY)

3 or more bytes in FIFO

6 or more bytes in FIFO

8 bytes in FIFO (Rx FULL)

Table 3a. Receiver FIFO interrupt fill

level(MR0(3)=1 (16 bytes)

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (Rx RDY)

8 or more bytes in FIFO

12 or more bytes in FIFO

16 bytes in FIFO (Rx FULL)

SC28L92 датащи(PDF) 22 Page - NXP Semiconductors

SC28L92 датащи(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL