Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

24

parity’ mode is programmed. In the special multi-drop mode it

selects the polarity of the A/D bit.

MR1A[1:0]—Channel A Bits Per Character Select

This field selects the number of data bits per character to be

transmitted and received. The character length does not include the

start, parity, and stop bits.

MR2A—Channel A Mode Register 2

MR2A is accessed when the Channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change

the pointer.

MR2 MODE REGISTER 2

Addr

Bit 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MR2A/B

CHANNEL MODE

Tx CONTROLS

RTS

CTS

ENABLE Tx

STOP BIT LENGTH

NOTE: Add 0.5 to binary codes 0–7 for 5 bit character lengths.

0x00

008

00 = Normal

0 = 0.563

4 = 0.813

8 = 1.563

C = 1.813

0x08

01 = Auto-Echo

0 = No

0 = No

1 = 0.625

5 = 0.875

9 = 1.625

D = 1.875

10 = Local loop

1 = Yes

1 = Yes

2 = 0.688

6 = 0.938

A = 1.688

E = 1.938

11 = Remote loop

3 = 0.750

7 = 1.000

B = 1.750

F = 2.000

NOTE:

Add 0.5 to values shown for 0–7 if channel is programmed for 5 bits/char.

MR2A[7:6]—Channel A Mode Select

Each channel of the DUART can operate in one of four modes.

MR2A[7:6] = 00 is the normal mode, with the transmitter and

receiver operating independently.

MR2A[7:6] = 01 places the channel in the automatic echo mode,

which automatically retransmits the received data. The following

conditions are true while in automatic echo mode:

1. Received data is reclocked and retransmitted on the TxDA

output.

2. The receive clock is used for the transmitter.

3. The receiver must be enabled, but the transmitter need not be

enabled.

4. The Channel A TxRDY and TxEMT status bits are inactive.

5. The received parity is checked, but is not regenerated for

transmission, i.e. transmitted parity bit is as received.

6. Character framing is checked, but the stop bits are retransmitted

as received.

7. A received break is echoed as received until the next valid start

bit is detected.

8. CPU to receiver communication continues normally, but the CPU

to transmitter link is disabled.

MR2A[7:6] = 10 selects local loop back diagnostic mode. In this

mode:

1. The transmitter output is internally connected to the receiver

input.

2. The transmit clock is used for the receiver.

3. The TxDA output is held High.

4. The RxDA input is ignored.

5. The transmitter must be enabled, but the receiver need not be

enabled.

6. CPU to transmitter and receiver communications continue

normally.

MR2A[7:6] = 11 selects remote loop back diagnostic mode. In this

mode:

1. Received data is reclocked and retransmitted on the TxDA

out-put.

2. The receive clock is used for the transmitter.

3. Received data is not sent to the local CPU, and the error status

conditions are inactive.

4. The received parity is not checked and is not regenerated for

transmission, i.e., transmitted parity is as received.

5. The receiver must be enabled.

6. Character framing is not checked, and the stop bits are

retransmitted as received.

7. A received break is echoed as received until the next valid start

bit is detected.

The user must exercise care when switching into and out of the

various modes. The selected mode will be activated immediately

upon mode selection, even if this occurs in the middle of a received

or transmitted character. Likewise, if a mode is deselected the

device will switch out of the mode immediately. An exception to this

is switching out of auto echo or remote loop back modes: if the

de-selection occurs just after the receiver has sampled the stop bit

(indicated in auto echo by assertion of RxRDY), and the transmitter

is enabled, the transmitter will remain in auto echo mode until the

entire stop has been re-transmitted.

MR2A[5]—Channel A Transmitter Request-to-Send Control

This bit controls the deactivation of the RTSAN output (OP0) by the

transmitter. This output is normally asserted by setting OPR[0] and

negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be

reset automatically one bit time after the characters in the Channel A

transmit shift register and in the TxFIFO, if any, are completely

transmitted including the programmed number of stop bits, if the

transmitter is not enabled.