SAF7113 datasheet(34/80 Pages) PHILIPS

34 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

8.11

RTCO output

The real-time control and status output signal contains

serial information about the actual system clock

(increment of the HPLL), subcarrier frequency, increment

and phase (via reset) of the FSC-PLL and PAL sequence

bit. The signal can be used for various applications in

external circuits, e.g. in a digital encoder to achieve clean

encoding. The SAF7113H supports RTC level 3.1 (see

external document

“RTC Functional Description”, available

on request).

8.12

RTS0, RTS1 terminals

These two pins are multi functional inputs/output

controlled by I2C-bus bits RTSE03 to RTSE00 and

RTSE13 to RTSE10, located in subaddress 12H;

see Tables 49 and 50.

The RTS0 terminal can be strapped to ground via a 3.3 k

Ω

resistor to change the I2C-bus slave address from default

4AH/4BH to 48H/49H (the strapping information is read

only during the reset sequence).

The RTS1 terminal can be configured as Data Output to

3-state (DOT) input by RTSE13 to RTSE10 = 0000 to

control the VPO port (bits 7 to 0) via hardware according

to Table 19.

Table 19 Digital output control via RTS1 (enabled by bits

RTSE13 to RTSE10 = 0)

BOUNDARY SCAN TEST

The SAF7113H has built in logic and 5 dedicated pins to

support boundary scan testing which allows board testing

without special hardware (nails). The SAF7113H follows

the

“IEEE Std. 1149.1 - Standard Test Access Port and

Boundary-Scan Architecture” set by the Joint Test Action

Group (JTAG) chaired by Philips.

The 5 special pins are Test Mode Select (TMS), Test

Clock (TCK), Test Reset (TRST), Test Data Input (TDI)

and Test Data Output (TDO).

The BST functions BYPASS, EXTEST, INTEST,

SAMPLE, CLAMP and IDCODE are all supported

(see Table 20). Details about the JTAG BST-TEST can be

found in the specification “

IEEE Std. 1149.1”. A file

containing the detailed Boundary Scan Description

Language (BSDL) description of the SAF7113H is

available on request.

OEYC

DOT

(RTS1)

VPO7 TO VPO0

active

Table 20 BST instructions supported by the SAF7113H

INSTRUCTION

DESCRIPTION

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO

when no test operation of the component is required.

EXTEST

This mandatory instruction allows testing of off-chip circuitry and board level interconnections.

SAMPLE

This mandatory instruction can be used to take a sample of the inputs during normal operation of

the component. It can also be used to preload data values into the latched outputs of the

boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This instruction addresses

the bypass register while the boundary scan register is in external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer, part number and

version number.

INTEST

This optional instruction allows testing of the internal logic (no support for customers available).

USER1

This private instruction allows testing by the manufacturer (no support for customers available).

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