SAF7113 datasheet(48/80 Pages) PHILIPS

48 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Table 22 Description of I2C-bus format; note 1

Notes

1. The SAF7113H supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbits/s).

2. If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.

CODE

DESCRIPTION

START condition

repeated START condition

Slave address W

0100 1010 (= 4AH, default) or 0100 1000 (= 48H, if pin RTS0 strapped to ground via a 3.3 k

Ω

resistor)

Slave address R

0100 1011 (= 4BH, default) or 0100 1001 (= 49H, if pin RTS0 strapped to ground via a 3.3 k

Ω

resistor)

ACK-s

acknowledge generated by the slave

ACK-m

acknowledge generated by the master

Subaddress

subaddress byte; see Table 24

Data

data byte; see Table 24; note 2

STOP condition

X = LSB slave

address

read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read

(the circuit is slave transmitter)

Subaddresses

00H chip version

read only

01H to 05H front-end part

read and write

06H to 13H decoder part

read and write

14H reserved

−

15H to 17H decoder part

read and write

18H to 1EH reserved

−

1FH video decoder status byte

read only

20H to 3FH reserved

−

40H to 5EH general purpose data slicer

read and write

5FH reserved

−

60H to 62H general purpose data slicer status read only

63H to FFH reserved

−

ACK-s

ACK-m

SLAVE ADDRESS R

MHB340

ACK-s

DATA

SUBADDRESS

SLAVE ADDRESS W

data transferred

(n bytes + acknowledge)

Fig.34 Read procedure (combined format).

SAF7113 датащи(PDF) 48 Page - NXP Semiconductors

SAF7113 датащи(HTML) 48 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL