SAF7113 datasheet(54/80 Pages) PHILIPS

54 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Fig.35 Mode 0; CVBS (automatic gain).

handbook, halfpage

MHB341

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.36 Mode 1; CVBS (automatic gain).

handbook, halfpage

MHB342

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.37 Mode 2; CVBS (automatic gain).

handbook, halfpage

MHB343

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.38 Mode 3; CVBS (automatic gain).

handbook, halfpage

MHB344

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.39 Mode 6; Y + C (gain channel 2 adjusted via

GAI2).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB345

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.40 Mode 7; Y + C (gain channel 2 adjusted via

GAI2).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB346

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.41 Mode 8; Y + C (gain channel 2 adapted to Y

gain).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

handbook, halfpage

MHB347

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

Fig.42 Mode 9; Y + C (gain channel 2 adapted to Y

gain).

I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1

(full luminance bandwidth).

MHB348

handbook, halfpage

AI22

AI21

AI12

AI11

AD2

AD1

CHROMA

LUMA

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