SAF7113 datasheet(27/80 Pages) PHILIPS

27 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Some details about data types:

• Active video (data type 15) component YUV 4 : 2 : 2

signal, 720 active pixels per line. Format and nominal

levels are given in Fig.23 and Table 13.

• Test line (data type 6), is similar to decoded YUV-data

as in active video, with two exceptions:

– vertical filter (chrominance comb filter for NTSC

standards, PAL-phase-error correction) within the

chrominance processing is disabled

– peaking and chrominance trap are bypassed within

the luminance processing, if I2C-bus bit VBLB is set.

This data type is defined for future enhancements; it

could be activated for lines containing standard test

signals within the vertical blanking period; currently

the most sources do not contain test lines.

This data type is available only in lines with VREF = 0,

see I2C-bus detail section, Table 45.

Format and nominal levels are given in Fig.23 and

Table 13.

• Raw samples (data type 7) oversampled CVBS-signal

for intercast applications; the data rate is 27 MHz.

The horizontal range is programmable via

HSB7 to HSB0, HSS7 to HSS0 and HDEL1 to HDEL0;

see I2C-bus section subaddresses 06H, 07H and 10H

and Tables 33, 34 and 46.

Format and nominal levels are given in Fig.24 and

Table 15.

• Sliced data (various standards, data types 0 to 5 and

8 to 14).

The format is given in Table 17.

The data type selections by LCR are overruled by setting

VIPB (subaddress 11H bit 1) to logic 1. This setting is

mainly intended for device production tests. The VPO-bus

carries the upper or lower 8 bits of the two ADCs

depending on the ADLSB (subaddress 13H bit 7) setting.

The output configuration is done via MODE3 to MODE0

settings (subaddress 02H bits 3 to 0, see Table 27). If the

YC-mode is selected, the VPO-bus carries the multiplexed

output signals of both ADCs, in CVBS-mode the output of

only one ADC. No timing reference codes are generated in

this mode.

Note: The LSBs (bit 0) of the ADCs are available on

pins RTS0 or RTS1. See Chapter 15, subaddress 12H for

details.

The SAV/EAV timing reference codes define start and end

of valid data regions.

Table 5

SAV/EAV format

BIT 7

BIT 6 (F)

BIT 5 (V)

BIT 4 (H)

BIT 3

(P3)

BIT 2

(P2)

BIT 1

(P1)

BIT 0

(P0)

ﬁeld bit

1st ﬁeld: F = 0;

2nd ﬁeld: F = 1;

for vertical timing

see Tables 6 and 7

vertical blanking bit

VBI: V = 1;

active video: V = 0;

for vertical timing

see Tables 6 and 7

H = 0 in SAV;

H = 1 in EAV

reserved; evaluation not

recommended (protection

bits according to ITU 656)

The generation of the H-bit and consequently the timing of

SAV/EAV corresponds to the selected data format. H = 0

during active data region. For all data formats excluding

data type 7 (raw data), the length of the active data region

is 1440 LLC. For the YUV 4:2:2 formats (data

types 15 and 6) every clock cycle within this range

contains valid data, see Table 13.

The sliced data stream (various standards, data types

0 to 5 and 8 to 14; see Table 17) contains also invalid

cycles marked as 00H.

The length of the raw data region (data type 7) is

programmable via HSB7 to HSB0 and HSS7 to HSS0

(subaddresses 06H and 07H; see Fig.24).

During horizontal blanking period between EAV and SAV

the ITU-blanking code sequence ‘-80-10-80-10-...’ is

transmitted.

The position of the F-bit is constant according to ITU 656

(see Tables 6 and 7).

The V-bit can be generated in four different ways

(see Tables 6 and 7) controlled via OFTS1 and OFTS0

(subaddress 10H, bits 7 and 6), VRLN (subaddress 10H,

bit 3) and LCR2 to LCR24 (subaddresses 41H to 57H).

F and V bits change synchronously with the EAV code.

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