SAF7113 datasheet(74/80 Pages) PHILIPS

74 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

16 I2C-BUS START SET-UP

The given values force the following behaviour of the SAF7113H:

• The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active

• Automatic field detection enabled, PAL BDGHI or NTSC M standard expected

• Standard ITU 656 output format enabled, VBI-data slicer disabled; see Table 74 note 2

• Contrast, brightness and saturation control in accordance with ITU standards

• Chrominance processing with nominal bandwidth (800 kHz).

Table 74 I2C-bus start set-up values

SUB

(HEX)

FUNCTION

NAME(1)

VALUES (BIN)

(HEX)

76543210

START

chip version

ID07 to ID04

read only

increment delay

X, X, X, X, IDEL3 to IDEL0

analog input control 1

FUSE1 and FUSE0, GUDL1 and GUDL0,

MODE3 to MODE0

11000000

analog input control 2

X, HLNRS, VBSL, WPOFF, HOLDG,

GAFIX, GAI28 and GAI18

00110011

analog input control 3

GAI17 to GAI10

analog input control 4

GAI27 to GAI20

horizontal sync start

HSB7 to HSB0

horizontal sync stop

HSS7 to HSS0

sync control

AUFD, FSEL, FOET, HTC1, HTC0, HPLL,

VNOI1 and VNOI0

10011000

luminance control

BYPS, PREF, BPSS1 and BPSS0, VBLB,

UPTCV, APER1 and APER0

00000001

luminance brightness

BRIG7 to BRIG0

luminance contrast

CONT7 to CONT0

chrominance saturation SATN7 to SATN0

chrominance hue

control

HUEC7 to HUEC0

chrominance control

CDTO, CSTD2 to CSTD0, DCCF, FCTC,

CHBW1 and CHBW0

00000001

chrominance gain

control

ACGC, CGAIN6 to CGAIN0

format/delay control

OFTS1 and OFTS0, HDEL1 and HDEL0,

VRLN, YDEL2 to YDEL0

00000000

output control 1

GPSW1, CM99, GPSW0, HLSEL, OEYC,

OERT, VIPB and COLO

00001100

output control 2

RTSE13 to RTSE10, RTSE03 to RTSE00

output control 3

ADLSB, X, X, OLDSB, FIDP, X,

AOSL1 and AOSL0

00000000

reserved

VGATE start

VSTA7 to VSTA0

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