SAF7113 datasheet(24/80 Pages) PHILIPS

24 / 80 page

2000 May 08

Philips Semiconductors

Product speciﬁcation

9-bit video input processor

SAF7113H

Table 2

Power-on control sequence

INTERNAL POWER-ON

CONTROL SEQUENCE

PIN OUTPUT STATUS

REMARKS

Directly after power-on

asynchronous reset

VPO7 to VPO0, RTCO, RTS0, RTS1,

SDA and LLC are in high-impedance state

direct switching to high-impedance for

20 to 200 ms

Synchronous reset

sequence

LLC and SDA become active;

VPO7 to VPO0, RTCO, RTS0 and RTS1 are

held in high-impedance state

internal reset sequence

Status after power-on

control sequence

VPO7 to VPO0, RTCO, RTS0 and RTS1 are

held in high-impedance state

after power-on (reset sequence) a complete

I2C-bus transmission is required

8.8

Multi-standard VBI data slicer

The multi-standard data slicer is a Vertical Blanking

Interval (VBI) and Full Field (FF) video data acquisition

block. In combination with software modules the slicer

acquires most existing formats of broadcast VBI and FF

data.

The implementation and programming model of the

multi-standard VBI data slicer is similar to the text slicer

built in the

“Multimedia Video Data Acquisition Circuit

SAA5284”.

The circuitry recovers the actual clock phase during the

clock-run-in-period, slices the data bits with the selected

data rate, and groups them into bytes. The clock

frequency, signals source, field frequency and accepted

error count must be defined via the I2C-bus in

subaddress 40H, AC1: bits D7 to D4.

Several standards can be selected per VBI line.

The supported VBI data standards are described in

Table 3.

The programming of the desired standards is done via

I2C-bus subaddresses 41H to 57H

(LCR2[7 : 0] to LCR24[7 : 0]); see detailed description in

Chapter 8.10. To adjust the slicers processing to the

signals source, there are offsets in horizontal and vertical

direction available via the I2C-bus in subaddresses 5BH

(bits 2 to 0), 59H (HOFF10 to HOFF0) and 5BH (bit 4),

5AH (VOFF8 to VOFF0). The formatting of the decoded

VBI data is done within the output interface to the

VPO-bus. For a detailed description of the sliced data

format see Table 17.

Table 3

Supported VBI standards

STANDARD TYPE

DATA RATE

(Mbits/s)

FRAMING CODE

WINDOW

HAM

CHECK

Teletext EuroWST, CCST

6.9375

27H

WST625

always

European closed caption

0.500

001

CC625

VPS

9951H

VPS

Wide screen signalling bits

1E3C1FH

WSS

US teletext (WST)

5.7272

27H

WST525

always

US closed caption (line 21)

0.503

001

CC525

Teletext

6.9375

programmable

general text

optional

VITC/EBU time codes (Europe)

1.8125

programmable

VITC625

VITC/SMPTE time codes (USA)

1.7898

programmable

VITC625

US NABTS

5.7272

programmable

NABTS

optional

MOJI (Japanese)

5.7272

programmable (A7H)

Japtext

Japanese format switch (L20/22)

programmable

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