Datasheet

8

002-37216 Rev. *B

2023-10-10

EZ-PD™ PAG2S-QZ integrated USB PD and secondary-side QR-ZVS

controller

Functional description

3

Functional description

3.1

System start-up

On power-up, the primary side start-up controller must start controlling the primary switch using its soft start

mechanism and provide sufficient current to charge the secondary-side output capacitor and the start-up current

required for EZ-PD™ PAG2S-QZ. The secondary output voltage is the input power supply source of PAG2S-QZ.

Once VBUS_IN voltage exceeds 3.3-V, PAG2S-QZ firmware will boot up and take control of the primary switch.

The PAG2S-QZ firmware boot up time is in the order of a few milliseconds.

Once the boot-up is complete, the firmware configures the error-amplifier to achieve the 5-V secondary output

and PAG2S-QZ will generate the PWM pulses accordingly. These pulses on PWM_DRV are coupled to the primary

start-up controller through a pulse transformer. On receiving the PWM pulses, the primary side start-up controller

is expected to synchronize its internal oscillator with the PWM pulses and switch from start-up mode to

secondary control mode. In secondary control mode, the primary switch is directly controlled by the PWM pulses

generated by PAG2S-QZ.

3.2

Modes of operation - SR

PAG2S-QZ supports synchronous rectification (SR) in both DCM and CCM modes. The SR sense block supports

negative sense detect and ZCD. Figure 3 through Figure 5 show the SR_GDRV functionality in QR/CrCM, valley

switching, and CCM modes. The SR controller has a turn-on propagation delay of 40 ns (typ) and a turn-off

propagation delay of 25 ns (typ).

Figure 3

SR_SEN and SR_GDRV in QR/CrCM mode

Time

Primary Current

Secondary Current

SR_SEN

Primary FET ON,

SR FET OFF

Primary FET ON,

SR FET OFF

Primary FET OFF,

SR FET ON

Primary FET OFF,

SR FET ON

Negative sense

detect

ZCD

Both FET OFF

SR_GDRV