Datasheet

6

002-37216 Rev. *B

2023-10-10

EZ-PD™ PAG2S-QZ integrated USB PD and secondary-side QR-ZVS

controller

Pinouts

Figure 2

32-pin QFN pin map

2.2

Pin description

2.2.1

SR_GDRV, SR_VSS, SR_SEN, SR_CPP, SR_CPN, SR_CAP

EZ-PD™ PAG2S-QZ senses the voltage across the synchronous rectifier NFET and appropriately controls the gate

driver to achieve optimum efficiency. It supports both standard NFET and logic-level NFET. PAG2S-QZ supports

synchronous rectification in QR/CrCM, valley switching, discontinuous conduction mode (DCM), and continuous

conduction mode (CCM). The SR sense block supports negative sense detect and ZCD. For solution having

resonance frequency on SR_DRAIN > 4 MHz, peak-detect is sensed via the SR_CAP pin by coupling SR_DRAIN to

SR_CAP via a 10-pF capacitor. If resonance frequency < 4 MHz, SR_CAP in must be left floating.

The gate driver (SR_GDRV) can be driven to internal VDDD or twice the VDDD to achieve lower RDS(ON) of the

external NFET. The gate driver can be driven to twice the VDDD using an internal doubler circuit, with the doubler

capacitor connected across the SR_CPP and SR_CPN pins. The source terminal of the SR FET must be connected

to the SR_VSS pin. The voltage at the drain node of the external NFET is sensed via SR_SEN using a resistive

divider.

2.2.2

FB, EA_OUT, CC_COMP_GPIOx

PAG2S-QZ integrates two error amplifier blocks which handle secondary-output sensing and regulation for both

constant voltage and constant current modes of operation. The error-amplifier output feeds into the internal

analog PWM block. The negative input of the error amplifier is the feedback (FB) pin and the positive input is an

internal voltage reference. Based on the desired VBUS output, the voltage at the FB pin will be changed using

internal current source/sink IDACs. An external compensation network is required between the FB and EA_OUT

pins, as shown in the application diagram (see Figure 1). Constant current operation makes use of an internal

LSCSA, the output of which feeds into an independent error amplifier as shown in functional block diagram.

Constant current mode regulation requires an external compensation network between CC_COMP_GPIOx and

EA_OUT as shown in Figure 1.

1

2

3

4

5

6

7

8

23

22

21

20

19

18

17

24

EPAD

VCCD

VDDD

VSS

VDDD_SR

SR_CPN

SR_CPP

VSS_SR

SR_GDRV

CSP

CSN

CC1

CC2

GPIO7

GPIO6

GPIO5

XRES