Datasheet

7

002-37216 Rev. *B

2023-10-10

EZ-PD™ PAG2S-QZ integrated USB PD and secondary-side QR-ZVS

controller

Pinouts

2.2.3

PWM_DRV

PAG2S-QZ supports an analog PWM generator, which modulates the pulse width of the primary-side FET in

voltage control mode. It generates a programmable ramp which is compared against the output of the error

amplifier to determine the PWM pulse width. The ramp is generated by sourcing current into an internal

capacitor; the source current is a programmable combination of a certain fixed current and the feed-forward

current. The PWM signal is transferred from the secondary side to the primary side through an external pulse edge

transformer.

2.2.4

VBUS_IN, VDDD, VCCD

PAG2S-QZ integrates a high-voltage regulator, which is powered from the VBUS_IN rail, the output of the

regulator powers the VDDD rail. The input to the regulator can range from 3.3-V minimum to 30-V maximum. This

regulator is intended to deliver PAG2S-QZ current consumption and is not expected to drive any external loads

or ICs. PAG2S-QZ also has an internal configurable discharge path for the VBUS_IN rail, which is used to discharge

the VBUS rail during negative voltage transitions. The discharge resistor strength is configurable through

firmware settings.

The regulated VDDD supply, is either used to directly power some internal analog blocks or further regulated

down to 1.8-V VCCD, which powers the majority of the core. VDDD and VCCD are brought out on to pins to connect

external capacitors for regulator stability; these are not meant to be used as power supplies.

2.2.5

VBUS_C, VBUS_CTRL

VBUS_C is used to monitor the voltage at the Type-C connector. VBUS_C has an internal configurable discharge

path, which is used to discharge the VBUS_C rail during negative voltage transitions. The discharge resistor

strength is configurable through firmware settings. The load switch is between VBUS_IN and VBUS_C. PAG2S-QZ

integrates an NFET gate driver to control this load switch. VBUS_CTRL is the output of this gate driver. There is

an optional slow turn-on feature which is meant to avoid sudden in-rush current.

2.2.6

CSP, CSN

PAG2S-QZ integrates a LSCSA to monitor the load current. CSP is the positive input pin for the LSCSA and CSN is

the negative input. Suggested Rsense for LSCSA is 5 m.

2.2.7

CC1, CC2

CC1 and CC2 are the communication channels for USB PD protocol. PAG2S-QZ integrates a USB PD transceiver

consisting of a transmitter (TX) and receiver (RX) that communicate Biphase Mark Code (BMC)-encoded data over

the Configuration Channel (CC) channels as per the USB PD standard. All communication is half-duplex. The

physical layer implements collision avoidance to minimize communication errors on the channel. This block

includes all termination resistors (Rp) and their switches as required by the USB PD specification.

To support active cable applications, PAG2S-QZ also integrates VCONN FETs to power the CC lines. An external

390-pF capacitor is required on both the CC1 and CC2 pins.

2.2.8

DP_GPIOx, DM_GPIOx

The DP and DM lines are the standard USB D+ and D- lines. PAG2S-QZ integrates a charge detect block, which

handles legacy charging protocols such as BC 1.2, Quick Charge, Apple Charging, and Samsung AFC. This block

integrates all the terminations required for these charging protocols; no external components are required. When

legacy charging is not required in the system, the same DP and DM lines can be re-used as standard GPIOs. The

charger detect block also supports impedance detection on DP/DM lines.

2.2.9

GPIOx, XRES

PAG2S-QZ has multiple GPIOs, out of which some are dedicated GPIOs and the rest are multiplexed with other

functionalities. These GPIOs support multiple drive modes and configurable threshold options. During power-on

and reset, the GPIOs are forced to the tristate so as not to crowbar any inputs and/or cause excess turn-on current.

The XRES pin can be used to initiate a reset; this pin is internally pulled HIGH and must be pulled LOW externally

to trigger a reset.