| поискавой системы для электроныых деталей |
|
WM8580 датащи(PDF) 31 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8580 датащи(HTML) 31 Page - Wolfson Microelectronics plc |
|
31 / 92 page ![]() Production Data WM8580 w PD Rev 4.0 February 2007 31 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 RDA2[7:0] 11111111 (0dB) Digital Attenuation control for DAC2 Right Channel (DACR2) in 0.5dB steps. See Table 23 R23 DIGITAL ATTENUATION DACR 2 17h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store RDA2 in intermediate latch (no change to output) 1 = Apply RDA2 and update attenuation on all channels. 7:0 LDA3[7:0] 11111111 (0dB) Digital Attenuation control for DAC3 Left Channel (DACL3) in 0.5dB steps. See Table 23 R24 DIGITAL ATTENUATION DACL3 18h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store LDA3 in intermediate latch (no change to output) 1 = Apply LDA3 and update attenuation on all channels. 7:0 RDA3[7:0] 11111111 (0dB) Digital Attenuation control for DAC3 Right Channel (DACR3) in 0.5dB steps. See Table 23 R25 DIGITAL ATTENUATION DACR3 19h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Apply RDA3 and update attenuation on all channels. 7:0 MASTDA[7:0] 11111111 (0dB) Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 23 R28 MASTER DIGITAL ATTENUATION 1Ch 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Apply gain and update attenuation on all channels. Table 22 Digital Attenuation Registers Note: The volume update circuit of the WM8580 has two sets of registers; LDAx and RDAx. These can be accessed individually, or simultaneously by writing to MASTDA - Master Digital Attenuation. Writing to MASTDA will overwrite the contents of LDAx and RDAx. L/RDAx[7:0] GAIN LEVEL 00(hex) - ∞ dB (mute) 01(hex) -127.5dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB Table 23 Digital Volume Control Gain Levels Setting the DACATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for DACATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R19 DAC CONTROL 5 13h 6 DACATC 0 Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations Table 24 DAC Attenuation Register (DACATC) The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This mechanism helps prevents pops and clicks during volume transitions, and is enabled by control bit DZCEN. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |