WM8580 datasheet(71/92 Pages) WOLFSON

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Production Data

WM8580

PD Rev 4.0 February 2007

MUTE

DESCRIPTION

Normal Operation

Mute DAC channels

Floating

MUTE is an output to indicate when Zero Detection occurs on all DACs

(ZFLAG).

H = detected, L = not detected.

Table 74 MUTE Pin Control Options

PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL

In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary

Audio Interface transmitter. This has the same operation as the PAIFTX_MS register bit. The

PAIFTX_RATE default settings of 256fs, and 64 BCLKs/LRCLK for BCLKSEL, are used in Hardware

Control Mode. See page 21 for more information on master mode operation.

SDIN

AUDIO INTERFACE (TX)

Slave

Master

Table 75 Audio Interface (Transmitter) Master Mode Hardware Mode Control

S/PDIF ERROR HANDLING

Should the incoming S/PDIF sub-frame contain a parity error or a bi-phase encoding error, it is

assumed the sub-frame has become corrupted. Similarly, if VALIDITY is detected as 1, it is assumed

the data within the S/PDIF frame is invalid. Under these conditions, the S/PDIF Receiver repeats the

last valid sample in place of the corrupted/invalid samples. (Note: For the S/PDIF receiver to S/PDIF

transmitter path, only VALIDITY errors will cause data to be overwritten – parity and bi-phase errors

have will not cause data to be overwritten).

POWERDOWN CONTROL

In Software Control Mode, the chip is powered-down by default. In Hardware Control Mode, the chip

is powered-up by default but can be powered up by setting the ALLPD(MFP7) input high. (Note that

in Software Control Mode, this pin takes the function of SAIF_LRCLK or GPO7).

ALLPD (MFP7)

Powerup

Powerdown

Table 76 Hardware Mode Powerdown Control

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