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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8580 датащи(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8580 датащи(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 92 page  WM8580 Production Data W PD Rev 4.0 February 2007 30 ZERO FLAG OUTPUT Each DAC channel has a “zero detect circuit” which detects when 1024 consecutive zero samples have been input. Should both channels of a DAC indicate a zero-detect (or if either DACPD or DMUTE is set for that DAC), then the Zero Flag for that DAC is asserted. The DZFM register bits determine which Zero Flag is visible on the MUTE and GPO pins. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R16 DAC CONTROL 2 10h 6:4 DZFM[2:0] 000 Selects the source for ZFLAG 000 - All DACs Zero Flag 001 - DAC1 Zero Flag 010 - DAC2 Zero Flag 011 - DAC3 Zero Flag 100 - ZFLAG = 0 101 - ZFLAG = 0 110 - ZFLAG = 0 111 - ZFLAG = 0 Table 20 DZFM Register INFINITE ZERO DETECT Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R16 DAC CONTROL 2 10h 7 IZD 0 Infinite zero detection circuit control and automute control 0 = Infinite zero detect automute disabled 1 = Infinite zero detect automute enabled Table 21 IZD Register With IZD enabled, applying 1024 consecutive zero input samples to a stereo input channel on any DAC will cause that stereo channel output to be muted. Mute will be removed as soon as either of those stereo channels receives a non-zero input. DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 LDA1[7:0] 11111111 (0dB) Digital Attenuation control for DAC1 Left Channel (DACL1) in 0.5dB steps. See Table 23 R20 DIGITAL ATTENUATION DACL 1 14h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store LDA1 in intermediate latch (no change to output) 1 = Apply LDA1 and update attenuation on all channels 7:0 RDA1[6:0] 11111111 (0dB) Digital Attenuation control for DAC1 Right Channel (DACR1) in 0.5dB steps. See Table 23 R21 DIGITAL ATTENUATION DACR 1 15h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store RDA1 in intermediate latch (no change to output) 1 = Apply RDA1 and update attenuation on all channels. 7:0 LDA2[7:0] 11111111 (0dB) Digital Attenuation control for DAC2 Left Channel (DACL2) in 0.5dB steps. See Table 23 R22 DIGITAL ATTENUATION DACL 2 16h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 = Store LDA2 in intermediate latch (no change to output) 1 = Apply LDA2 and update attenuation on all channels. |
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