WM8580 datasheet(41/92 Pages) WOLFSON

номер детали	WM8580

подробное описание детали	Multichannel CODEC with S/PDIF Transceiver

PDF	92 Pages

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производитель	WOLFSON [Wolfson Microelectronics plc]

домашняя страница	http://www.wolfsonmicro.com

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Production Data

WM8580

PD Rev 4.0 February 2007

S/PDIF INTERFACES

The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK,

PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK, but both PLLACLK and PLLBCLK

are unavailable in user mode when the S/PDIF receiver is active. If the digital routing has been

configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is

automatically selected.

The rate at which the S/PDIF Transmitter operates at is determined by the S/PDIF Transmitter Rate

module. It calculates the rate based on the digital routing setup. When sourcing from the S/PDIF

Receiver (default), the SFRM_CLK is used in the rate calculation. When sourcing from the PAIF

Receiver, PAIFRX_LRCLK is used in the rate calculation. When sourcing from the SAIF Receiver,

SAIFRX_LRCLK is used in the rate calculation. When sourcing the ADC, the rate is determined by

either the PAIFTX_LRCLK (if the PAIF Transmitter also sources the ADC) or the ADC_RATE

Figure 28 S/PDIF Clock Selection

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKSEL

08h

5:4

TX_CLKSEL

S/PDIF Transmitter clock source

00 = ADCMCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

Table 35 S/PDIF Transmitter Clock Control

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