WM8580 datasheet(52/92 Pages) WOLFSON

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WM8580

Production Data

PD Rev 4.0 February 2007

OSC

CLK

(MHz)

PRE-

SCALE_X

S/PDIF RECEIVER

SAMPLE RATE(S) (kHz)

(MHz)

PLLB_N

(Hex)

PLLB_K

(Hex)

COMMENT

11.2896

32 / 44.1 / 48 / 88.2 / 96

11.2896 94.3104 8.3537

16A3B3

Set N, K

11.2896

192

11.2896 98.304 8.7075

2D4766

Set N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Default Setting

192

98.304

8.192

C49BA

Set N, K

12.288

32 / 44.1 / 48 / 88.2 / 96

12.288 94.3104 7.675

2B3333

Set K

12.288

192

12.288

98.304

Set N, K

19.2

32 / 44.1 / 48 / 88.2 / 96

9.6

94.3104 9.824

346C6A

Set Prescales, N, K

19.2

192

9.6

98.304

10.24

F5C28

Set Prescales, N, K

32 / 44.1 / 48 / 88.2 / 96

94.3104 7.8592

36FD21

Set Prescales

192

98.304

8.192

C49BA

Set Prescales, N, K

32 / 44.1 / 48 / 88.2 / 96

13.5

94.3104 6.986

3F19E5

Set Prescales, N, K

192

13.5

98.304 7.2818

1208A5

Set Prescales, K

Table 47 S/PDIF Receive Mode PLLB Initial Configuration Examples

The recommended configuration sequences are as follows:

TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:

Write

appropriate

calculated

values

(relative

oscillator

frequency)

PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K for 32/44.1/48/88.2/96kHz

(modes 2/3/4) S/PDIF receiver sample rate operation.

Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits.

Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF

sample frequency and clocking mode.

If indicated sample rate is 192kHz, write appropriate calculated values (relative to

oscillator frequency) to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K (as

appropriate) for 192kHz (mode 1) S/PDIF receiver sample rate operation.

TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR

FROM MODE 1 (192KHZ):

Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz

(mode 1)) will be flagged to the application processor via the INT interrupt flag. The application

processor must then read the Interrupt Status Register. If the UPD_REC_FREQ flag is set, indicating

that the clocking mode has changed, proceed as follows:

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF

sample rate frequency and clocking mode.

Write

appropriate

calculated

values

(relative

oscillator

frequency)

PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K based on indicated recovered

S/PDIF sample frequency and clocking mode.

This procedure is only strictly necessary when switching to or from 192kHz (mode 1) because the

PRESCALE_A,

PRESCALE_B,

PLLB_N

and

PLLB_K

values

are

the

same

for

32/44.1/48/88.2/96kHz (modes 2/3/4) sample rate operation. It is, however, good interrupt service

routine practice to write the appropriate PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K values

when every clocking mode change is detected.

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