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WM8580 датащи(PDF) 65 Page - Wolfson Microelectronics plc |
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WM8580 датащи(HTML) 65 Page - Wolfson Microelectronics plc |
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65 / 92 page ![]() Production Data WM8580 w PD Rev 4.0 February 2007 65 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3:0 GPO1OP[3:0] 0000 R38 GPO1 26h 7:4 GPO2OP[3:0] 0001 3:0 GPO3OP[3:0] 0010 R39 GPO2 27h 7:4 GPO4OP[3:0] 0011 3:0 GPO5OP[3:0] 0100 R40 GPO3 28h 7:4 GPO6OP[3:0] 0101 3:0 GPO7OP[3:0] 0110 R41 GPO4 29h 7:4 GPO8OP[3:0] 0111 3:0 GPO9OP[3:0] 1000 R42 GPO5 2Ah 7:4 GPO10OP [3:0] 1001 0000 = INTB 0001 = V 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = REC_FREQ192 1010 = ZFLAG 1011 = NON_AUDIO 1100 = CPY_N 1101 = DEEMP 1110 = Set GPO as S/PDIF input (CMOS-compatible input). Only applicable for GPO3/4/5. 1111 = Set GPO as S/PDIF input (‘comparator’ input for AC coupled consumer S/PDIF signals). Only applicable for GPO3/4/5 Table 66 GPO Control Registers POWERDOWN MODES The WM8580 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use. DACPD can be overwritten by setting ALLDACPD to powerdown all DACs The S/PDIF transmitter is powered down by setting SPDIFTXD. Setting SPDIFRXD powers down the S/PDIF receiver. The PLL, Oscillator and S/PDIF clock recovery circuits are powered down by setting PLLPD, OSCPD and SPDIFPD respectively. Setting all of ADCPD, DACPD[2:0], SPDIFTXD, SPDIFRXD and OUTPD[3:0] will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PWDN. Setting PWDN will override all other powerdown control bits. It is recommended that the ADC and DAC are powered down before setting PWDN. The default is for all powerdown bits to be set except OSCPD and PWDN. |
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