WM8580 datasheet(85/92 Pages) WOLFSON

85 / 92 page

Production Data

WM8580

PD Rev 4.0 February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

UNLOCK

Indicates that the S/PDIF Clock Recovery circuit is unlocked or

that the input S/PDIF signal is not present.

0 = Locked onto incoming S/PDIF stream.

1 = Not locked to the incoming S/PDIF stream or the incoming

S/PDIF stream is not present.

PWDN

Chip Powerdown Control (works in tandem with the other

powerdown registers):

0 = All digital circuits running, outputs are active

1 = All digital circuits in power save mode, outputs muted

ADCPD

ADC powerdown:

0 = ADC enabled

1 = ADC disabled

4:2

DACPD[2:0]

111

DAC powerdowns (0 = DAC enabled, 1 = DAC disabled)

DACPD[0] = DAC1

DACPD[1] = DAC2

DACPD[2] = DAC3

R50

PWRDN 1

32h

ALLDACPD

Overrides DACPD[3:0]

0 = DACs under control of DACPD[3:0]

1= All DACs are disabled.

OSCPD

OSC power down

0 = OSC enabled

1 = OSC disabled

PLLAPD

0 = PLLA enabled

1 = PLLA disabled

PLLBPD

0 = PLLB enable

1 = PLLB disable

SPDIFPD

S/PDIF Clock Recovery PowerDown

0 = S/PDIF enabled

1 = S/PDIF disabled

SPDIFTXD

S/PDIF Transmitter powerdown

0 = S/PDIF Transmitter enabled

1 = S/PDIF Transmitter disabled

R51

PWRDN 2

33h

SPDIFRXD

S/PDIF Receiver powerdown

0 = S/PDIF Receiver enabled

1 = S/PDIF Receiver disabled

2:0

READMUX

[2:0]

000

Determines which status register is to be read back:

000 = Error Register

001 = Channel Status Register 1

010 = Channel Status Register 2

011 = Channel Status Register 3

100 = Channel Status Register 4

101 = Channel Status Register 5

110 = S/PDIF Status Register

CONTREAD

Continuous Read Enable.

0 = Continuous read-back mode disabled

1 = Continuous read-back mode enabled

R52

READBACK

34h

READEN

Read-back mode enable.

0 = read-back mode disabled

1 = read-back mode enabled

R53

RESET

35h

8:0

RESET

n/a

Writing to this register will apply a reset to the device registers.

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