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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RT3624LE датащи(PDF) 18 Page - Richtek Technology Corporation |
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RT3624LE датащи(HTML) 18 Page - Richtek Technology Corporation |
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18 / 48 page  RT3624LE Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS3624LE-00 April 2022 18 ISEN4N ISEN4P PWM4 4 3 RT3624LE 50 VCC 47 R2 2.2 Ω C2 4.7µF 5V ISEN3N ISEN3P PWM3 48 1 2 VCC PWM BOOT UGATE PHASE LGATE PGND RT9610C EN DRVEN C52 1µF 5V VIN C53 0.1µF C54 L6 R68 Q11 Q12 R69 C57 0.1µF R66 2.2 C56 R67 R71 680 Ω Ω C55 R70 Optional Optional C58 0.1µF R77 10k Figure 3. 3-Phases Operation Setting Rail Disable Pulling ISEN1N to VCC programs GTUS rail disabled. The unused ISENxP pins are recommended to connect to VCC and the unused PWMx pins can be floating. Pulling ISENA1N to VCC programs VCCSA rail disabled. The unused ISENAxP pins are recommended to connect to VCC and the unused PWMAx pins can be floating. Pulling the PSYS pin to (VCC – 0.5V) programs input power domain rail disabled. RT3624LE rejects any commands to the input power domain rail. The unused ISENP_AUX pin and ISENN_AUX pin are recommended to connect to VCC. Acoustic Noise Suppression The RT3624LE supports acoustic noise suppression function for reducing acoustic noise induced by piezoelectric effect from MLCC. As output voltage transition occurs, especially in dynamic VID, the vibrating MLCC produces acoustic noise if the vibrating frequency falls into audible band and the noise level is related to the output voltage transition amplitude ∆V. Therefore, the RT3624LE adopts acoustic noise suppression function which is enabled by pulling ANS pin to VCC to reduce ∆V when SetVID down and SetVID Decay down in DEM mode. PIN-SETTING Mechanism The RT3624LE provides multiple parameters for platform setting and BOM optimization. These parameters can be set through SETx and TSEN pins. The RT3624LE adopts two-step PIN-SETTING mechanism to maximize IC pin utilization. Figure 4 illustrates this operating mechanism for SETx. The Vdivider and Vcurrent can be represented as follows: R2 R1 R2 R1 80uA 3.2V R2 R1 R2 V 3.2V R2 R1 R2 V current divider + × × + × + = × + = VREF = 3.2V R1 R2 SETx 80 μA SETx Divider-Register ADC SETx IXR-Register Figure 4. Operating Mechanism for SETx Divider-Register and IXR-Register set the specified functions. For example, Divider-Register of SET1 sets VBOOT and ICCMAX of GTUS rail; IXR-Register of SET1 sets VCCSA rail ICCMAX. All setting functions are summarized in Table 1. |
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