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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RT3624LE датащи(PDF) 36 Page - Richtek Technology Corporation |
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RT3624LE датащи(HTML) 36 Page - Richtek Technology Corporation |
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36 / 48 page  RT3624LE Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS3624LE-00 April 2022 36 Load-line Setting (RLL) An output voltage load-line (Adaptive Voltage Positioning) is specified in CPU VR for power saving and output capacitance reduction. The characteristic of load-line is that the output voltage decreases by an amount proportional to the increasing loading current. The slope between output voltage and loading current (RLL) is shown in Figure 13. Figure 14 shows the voltage and current loop circuits of the RT3624LE for the load-line control. The detailed equation is described as below RLL= Current Loop Gain Voltage Loop Gain = DCR 680 Ω ×RIMON,EQ× Ai REA2 REA1 × 3 2 Ai is current gain. REA2 REA1 is ERROR AMP gain and suggested to be greater than 2 for better transient response. RLL can be programmed by Ai and REA2 REA1 . Ai can be selected by PIN-SETTING of Ai[1:0] as listed in Table 12. VGTUS VID RLL x ICCMAX Load-line=-RLL ICCMAX Loading Current Figure 13. Load-line (Droop) + - REA1 VID Cx Rx Lx DCR IL1~IL4 ISENxN ISENxP (sum of ICS,PERx) - + - Voltage Loop RIMON,EQ IMON RNTC VREF + - Gm TON GEN/ Driver Interface PWM CMP Current Loop ERROR AMP REA2 Ai VGTUS Figure 14. Voltage Loop and Current Loop for Loadline Table 12. PIN-SETTING of Ai Ai[1:0] Current Gain Setting 00 0.25 01 0.50 10 0.75 11 1.00 |
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