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RT3624LE датащи(PDF) 4 Page - Richtek Technology Corporation

номер детали RT3624LE
подробное описание детали  Dual Channel PWM Controller for IMVP9.1 CPU Core Power Supply
PDF  48 Pages
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производитель  RICHTEK [Richtek Technology Corporation]
домашняя страница  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT3624LE датащи(HTML) 4 Page - Richtek Technology Corporation

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RT3624LE
Copyright © 2022 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
www.richtek.com
DS3624LE-00
April
2022
4
Pin No.
Pin Name
Pin Function
29
PSYS
System input power monitor. Place the PSYS resistor as close to the IC as
possible. The input power domain(SVID Address 0x0Dh) rail can be
disabled by pulling the voltage at the PSYS pin > (VCC – 0.5V). RT3624LE
rejects any commands to the input power domain rail. If the platform
doesn't support PSYS function, it is recommended to connect PSYS pin to
GND to avoid affecting system performance.
30
RGNDA
Return ground for VCCSA rail VR. This pin is the negative node of the
differential remote voltage sensing.
31
VSENA
VCCSA rail VR voltage sense input. This pin is connected to the terminal of
VCCSA rail VR output voltage.
32
COMPA
VCCSA rail VR compensation. This pin is an error amplifier output pin.
33
FBA
Negative input of the error amplifier. This pin is for VCCSA rail VR output
voltage feedback to controller.
37, 34
ISENA[1:2]N
Negative inputs to current-sense amplifier for Phase 1 to 2 of VR VCCSA
rail.
36, 35
ISENA[1:2]P
Positive inputs to current-sense amplifier for Phase 1 to 2 of VR VCCSA
rail.
38
ISENP_AUX
Positive input to current-sense amplifier of VR AUX rail.
39
ISENN_AUX
Negative input to current-sense amplifier of VR AUX rail.
40
DBLR_PS
External driver mode control. As PS4 command is received, this pin is in
high state. This pin can work with RT9637 to drive two power stages with
single PWM signal. As PS0 command is received, this pin is in low state.
As PS1 command is received, this pin is in floating state. As PS2/3
command is received, this pin is in high state.
41
DRVEN
External driver mode control. As PS4 command is received, this pin is in
low state. The output high level is VCC.
42
DRVEN_F
External driver mode control. As PS4 command is received, this pin is in
floating state. The output high level is VCC.
44, 43
PWMA[1:2]
PWM outputs for VCCSA rail VR. The tri-state window = 1.6V to 2.2V.
45, 46, 48, 47
PWM[1:4]
PWM outputs for GTUS rail VR. The tri-state window = 1.6V to 2.2V.
49
ANS_EN
Acoustic Noise Suppression function setting. When the pin is pulled to
VCC, this function can be enabled. This pin is not allowed to be floating.
50
VCC
Controller power supply. Connect this pin to 5V and place an RC filter, R =
2.2
Ω and C = 4.7µF. The decoupling capacitor should be placed as close
to PWM controller as possible. The recommended size of RVCC is 0603.
51
VRON
VR enable control input.
52
VIN/VSYS
VIN/VSYS input pin. Connect a low pass filter to this pin to set on-time.
53
(Exposed Pad)
GND
Ground. The Exposed Pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.



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