RT3624LE datasheet(7/48 Pages) RICHTEK

7 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

DS3624LE-00

April

2022

www.richtek.com

Loop Control/Protection Logic

It controls power-on/off sequence, protections, power

state transition, and PWM sequence.

DAC

The DAC generates a reference VID voltage according

to the VID code sent by Control Logic. According to

setVID command, Control Logic dynamically changes

VID voltage to the target voltage with required slew

rate.

ERROR AMP

The ERROR AMP inverts and amplifies the difference

between output voltage and VID with externally set

finite DC gain. The output signal is COMP for PWM

trigger.

PER CSGM

The PER CSGM senses per-phase inductor current.

The outputs are used for loop response, current

balance, zero current detection, current reporting and

over-current protection.

SUM CSGM

The SUM CSGM senses total inductor current with

RIMON gain adjustment. SUM CSGM output current

ratio can also be set by PIN-SETTING(Ai[1:0]). It helps

wide application range of DCR and load-line. SUM

CSGM output is used for PWM trigger.

RAMP

The RAMP helps loop stability and transient response.

PWM CMP

The PWM comparator compares COMP signal with

sum current signal based on RAMP to trigger PWM.

Offset Cancellation

The offset cancellation is based on VID, COMP voltage

and current signal from SUM CSGM to control output

voltage accurately.

Current Balance

Per-phase current sense signal is compared with

sensed average current. The comparison result adjusts

each phase PWM width to optimize current and thermal

balance.

Zero Current Detection

Detects whether each phase current crosses zero

current. The result is used for DEM power saving and

overshoot reduction (anti-overshoot function).

AQR/ANTIOVS

The AQR is a new generation of quick response

mechanism (Adaptive Quick Response, AQR) which

detects loading rising edge and allows all PWMs to turn

on. The PWM pulse width triggered by AQR is adaptive

to loading level. The AQR trigger level can be set by

PIN-SETTING. ANTIOVS can help overshoot reduction

which detects loading falling edge and forces all PWMs

in tri-state until the zero current is detected.

OCP

The

RT3624LE

has

two

over-current

protection

mechanisms, sum OCP and OC limit.

OVP

The over-voltage protection threshold is linked to VID.

Please refer to classification table and waveform in

Table 17, Figure 23 and Figure 24.

UVP

When the output voltage is lower than VID-650mV with

µs filter time, UVP is triggered and all PWMs are in

tri-state to turn off high-side power MOSFETs.

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