RT3624LE datasheet(46/48 Pages) RICHTEK

46 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

www.richtek.com

DS3624LE-00

April

2022

Table 18. Summary of UVP and OCP Protection

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding

airflow, and the difference between the junction and

ambient

temperatures.

The

maximum

power

dissipation can be calculated using the following

formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature,

TA is the ambient temperature, and

θJA is the

junction-to-ambient thermal resistance.

For continuous operation, the maximum operating

junction temperature indicated under Recommended

Operating Conditions is 125

°C. The junction-to-

ambient thermal resistance,

θJA, is highly package

dependent. For a WQFN-52L 6x6 package, the thermal

resistance,

θJA, is 26.5°C/W on a standard JEDEC

51-7 high effective-thermal-conductivity four-layer test

board. The maximum power dissipation at TA = 25

°C

can be calculated as below :

PD(MAX) = (125

°C − 25°C) / (26.5°C/W) = 3.77W for a

WQFN-52L 6x6 package.

The maximum power dissipation depends on the

operating ambient temperature for the fixed TJ(MAX)

and the thermal resistance,

θJA. The derating curves in

Figure 26 allows the designer to see the effect of rising

ambient

temperature

the

maximum

power

dissipation.

Figure 26. Derating Curve of Maximum Power

Dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Protection

Type

Protection Threshold

Protection

Flag

Protection

Action

DVID

mask

time

Protection

Reset

Sum OCP

for PS0

ISUM_OC,PS0=KSOCP×VIMON

ICCMAX×

RCS

DCR

RIMON,EQ

VREF=2V

PWM

tri-state,

VR_READY

latched low

DVID+

80us

VCC/

VRON

Toggle

Sum OCP

for

non

PS0

ISUM_OC,PS1,2,3=KSOCP1×VIMONICCMAX×

RCS

DCR

RIMON,EQ

VREF=2V

UVP

VID-650mV

VREF=1.5V

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