CS5535 datasheet(257/555 Pages) NSC

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ATAC Register Descriptions (Continued)

ATAC_CH0D0_DMA Bit Descriptions

Bit

Name

Description

63:32

RSVD

Reserved. Set to 0.

If bit 20 = 0, Multi-word DMA.

Settings for:

Multi-word DMA Mode 0 = 7F0FFFF3h

Multi-word DMA Mode 1 = 7F035352h

Multi-word DMA Mode 2 = 7F024241h

PIO_FORM

PIO Mode Format.

0: Format 0.

1: Format 1.

30:24

MODE66_SEL

Mode 66 Select: Set to 7Fh for 66 MHz system clock.

23:21

RSVD

Reserved. Set to 0.

DMA_SEL

DMA Select. DMA operation.

0: Multi-word DMA.

1: Ultra DMA.

19:16

tKR

IDE_IOR# Recovery Time (4-bit). Value + 1 cycle.

15:12

tDR

IDE_IOR# Pulse Width. Value + 1 cycle.

11:8

tKW

IDE_IOW# Recovery Time (4-bit). Value + 1 cycle.

7:4

tDW

IDE_IOW# Pulse Width. Value + 1 cycle.

3:0

IDE_CS0#/CS1# to IDE_IOR#/IOW# Setup; IDE_CS0#/CS1# Setup to

IDE_DACK0#/DACK1#.

If bit 20 = 1, Ultra DMA.

Settings for:

Ultra DMA Mode 0 = 7F7436A1h

Ultra DMA Mode 1 = 7F733481h

Ultra DMA Mode 2 = 7F723261h

Ultra DMA Mode 3 = 7F713161h

Ultra DMA Mode 4 = 7F703061h

PIO_FORM

PIO Mode Format.

0: Format 0.

1: Format 1.

30:24

MODE66_SEL

Mode 66 Select: Set to 7Fh for 66 MHz system clock.

23:21

RSVD

Reserved. Set to 011. Will read back as 011.

DMA_SEL

DMA Select. DMA operation.

0: Multi-word DMA.

1: Ultra DMA.

19:16

tCRC

CRC Setup UDMA in IDE_DACK#. Value + 1 cycle (for host terminate CRC setup =

tMLI + tSS).

15:12

tSS

UDMA Out. Value + 1 cycle.

11:8

tCYC

Data Setup and Cycle Time UDMA Out. Value + 2 cycles.

7:4

tRP

Ready to Pause Time. Value + 1 cycle.

Note:

tRFS + 1 tRP on next clock.

3:0

tACK

IDE_CS0#/CS1# Setup to IDE_DACK0#/DACK1#. Value + 1 cycle.

Note:

66 MHz clock cycles. The ‘value’ that is entered is the desired number of 66 MHz clock cycles in hexadecimal;

the actual parameter timing generated by that entry is the entered ‘value’ plus the indicated number of ‘cycles’

(‘n’) as listed in the description of that parameter.

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