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CS5535 датащи(PDF) 254 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 254 Page - National Semiconductor (TI) |
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254 / 555 page ![]() www.national.com 254 Revision 0.8 ATAC Register Descriptions (Continued) 5.4.2 ATAC Specific MSRs 5.4.2.1 I/O Base Address (ATAC_IO_BAR) This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [2:0] are read only (001), indicating an 8-byte I/O address range. 5.4.2.2 Reset Decode (ATAC_RESET) MSR Address 51300008h Type R/W Reset Value 00000000_00000001h ATAC_IO_BAR Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD BM_IDE_BAR ADD_RNG ATAC_IO_BAR Bit Descriptions Bit Name Description 63:33 RSVD Reserved. Write as 0. Return 0 on read. 32 BM_IDE_BAR_ EN Bus Mastering IDE Base Address Enable. This bit should be set to enable access to the native register set after the base address has been set. 0: Disable (i.e., cannot access native registers in ATAC). 1: Enable (normal operation). 31:17 RSVD Reserved. Write to 0. Return 0 on read. 16:3 BM_IDE_BAR Bus Mastering IDE Base Address. These bits form the base address of the ATAC native register set. Users may write the full address, including bits [2:0], knowing that bits [2:0] will drop off and be assumed as 000. 2:0 ADD_RNG (RO) Address Range (Read Only). Hard wired to 001. This indicates that the I/O base address is in units of bytes. MSR Address 51300010h Type R/W Reset Value 00000000_00000000h ATAC_RESET Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD |
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